第4章 数字逻辑单元设计

1、process(clk,clr,pre,c) begin if(clr=1) then q_tmp=0; elsif(pre=1) then q_tmp=1; elsif rising_edge(clk) then if(ce=1) then q_tmp=d; else q_tmp=q_tmp; end if; end if; end process;end rtl;输入输入输出输出RSCEJKCQ1XXXX001XXX1000XXX无变化无变化00100X无变化无变化00101000111翻转翻转001101 if(r=1) then q_tmp=0; elsif(s=1) then q_t

2、mp=1; elsif rising_edge(clk) then if(ce=0) then q_tmp=q_tmp; else if(j=0 and k=1) then q_tmp=0; elsif(j=1 and k=0) then q_tmp=1; elsif(j=1 and k=1) then q_tmp=not q_tmp; end if; end if; end process;end rtl;输入输出RSCQ00无变化01110011无变化process(clk) begin if rising_edge(clk)then if (s = 1 and r = 0) then q

3、_tmp=1; elsif (s=0 and r=1) then q_tmp=0; elsif (s=0 and r=0) then q_tmp=q_tmp; else null; end if; end if; end process; end rtl;architecture Behavioral of mod5cnt isbegin process(clk,clr) begin if(clr=1) then q=000; elsif(rising_edge(clk) then if(q=100) then q=000; else q=q + 1; end if; end if; end

4、process;end Behavioral;architecture Behavioral of clkdiv issignal q : std_logic_vector(24 downto 0);begin process(clr,clk) begin if(clr=1) then q0); elsif(rising_edge(clk) then q = q + 1; end if; end process; clk190 = q(17); -190Hz clk48 = q(19); -47.7Hzend Behavioral;architecture Behavioral of ring

5、_shiftreg4 isbegin process(clr,clk) begin if(clr=1) then q=0001; elsif(rising_edge(clk) then q(3) = q(0); q(2 downto 0) = q(3 downto 1); end if; end process;end Behavioral;architecture Behavioral of debounce4 issignal delay1,delay2,delay3 : std_logic_vector(3 downto 0);begin process(cclk,clr,inp) be

6、gin if(clr=1) then delay1=0000; delay2=0000; delay3=0000; elsif(rising_edge(cclk) then delay1=inp; delay2=delay1; delay3=delay2; end if; end process; outp=delay1 and delay2 and delay3; end Behavioral;architecture Behavioral of clock_pluse issignal delay1,delay2,delay3 : std_logic;begin process(clr,c

7、clk) begin if(clr=1) then delay1=0; delay2=0; delay3=0; elsif(rising_edge(cclk) then delay1=inp; delay2=delay1; delay3=delay2; end if; end process; outp=delay1 and delay2 and (not delay3);end Behavioral;%100周期占空占空比architecture Behavioral of pwm4 issignal count : STD_LOGIC_VECTOR (3 downto 0);signal

8、set,reset : std_logic;Beginset = not (count(0) or count(1) or count(2) or count(3); process(clk,clr) begin if(clr=1) then count=0000;elsif(rising_edge(clk) then if(count=period1-1) then count=0000; else count=count + 1; end if; end if; end process;process(clk)begin if(rising_edge(clk) then if(set=1)

9、 then pwm=1; end if; if(reset=1) then pwm=0; end if; end if;end process;end Behavioral;图4.16 ROM的结构图图4.17 单端口RAM的结构十进制数十进制数二进制码二进制码Gray码码Johnson码码One-hot吗吗000000000000110010010010102010011011100301101011110004100110510111161101017111100architecture Behavioral of seqdeta istype state is(s0,s1,s2,s3,s

10、4); -状态声明signal present_state,next_state : state; beginprocess(clr,clk)begin if(clr=1) then -状态寄存器 present_state=s0; elsif rising_edge(clk) then present_state=next_state; end if;end process;architecture Behavioral of seqdetb istype state is(s0,s1,s2,s3); -定义状态signal present_state,next_state : state; beginprocess(clr,clk) -状态寄存器begin if(clr=1) then present_state=s0; elsif rising_edge(clk) t