400HZ中频电源

1、百度文库让每个人平等地捉升口我10400Hz中频电源的设计摘要：随着科学技术的发展以及提高我国国防能力的需要，对军事设施的技术改造已 被列为军事技术改造中的重点。中频电源指输出频率为400Hz的电源，它可以为动力系 统及导航与武备系统供电。传统的400Hz中频电源体积大，输出波形不稳定。本文所设 计的400Hz中频电源釆用了稳定的石英晶体振荡回路，通过分频电路、积分电路、放大 电路和检波电路及单片机系统，控制其最后的输出电压，实现了电压的稳定输出，具有 体积小、功率大和波形无失真等优点，有着广泛的用途和良好的发展前景。关键词：中频电源 单片机 正弦波The Design of the 400H

2、z Intermediate Frequency Power SupplyAbstract:With the development of technology and the increasing requirements of nationaldefense, the technical innovation on military establishment has become the key part in militaryaffairs. The power supply of intermediate frequency whose output frequency is 400

3、Hz canprovide power for the system of motion, navigation and weapon equipments. The wave outputfrom traditional power supply of intermediate frequency is unsteady. The design in this textadopt the oscillating circuit based on quartz crystal oscillator, and the hardware made up of thedivided frequenc

4、y circuit, integral circuit, amplifying circuit, demodulation circuit and SCM( Single Chip Microcomputer ) system can control the output voltage at the end The circuitrealizes the steady output of voltage, and the characteristics such as small volume, high powerand no distortion of wave make it wide

5、ly used and have a bright future.Keywords:The powersupply of intermediate frequency SCM Sine Wave目录1引言.12设计要求.13 400Hz中频电源的硬件原理与设计 .1振荡电路.2百度文邮-让每个人平零地捉升口我11分频电路.2积分电路.4放大电路.6控制电路的原理与设计方案.95测试结果.116结论.12参考文献.13致谢.14附录系统电路图.14英文资料及中文翻译.15400Hz中频电源，可广泛应用于舰艇，飞机及机载设备以及工业控制设备，例如， 旋转变压器是一种信号检测设备，通过角度的改变，可

6、实现输出电压的改变，进而为控 制设备提供控制信号。利用400Hz中频电源给旋转变压器供电，可以实现系统电信号的 控制，将非电量转变成了电量。在航天航空设备中，中频电源性能的优劣和可翥性将决定着航行器的安全行驶与战 斗力的发挥。新型中频电源自动控制系统具有电路简单，可以实现复杂的控制，控制灵 活且具有通用性的优点。当电源本身特性发生变化时候，完全可以通过对软件参数进行 修改来对电路进行改动，可以为进一步实现集中控制带来方便。采用新型数字控制系统 后，中频电源具有启动平稳、运行稳定、控制精度高、调试与维修方便、体积小等优点。2设计要求百度文邮-让每个人平等地捉升口我22(1)实现输出频率为稳定的4

7、00Hz正弦波。(2)输出波形没有明显失真。(3)输出电压为25V65V连续可调(有效值)。3 400Hz中频电源的硬件原理与设计4MHz信号基准电源，通过分频电路进行分频得到400Hz的信号，经过积分电路将方 波转化为正弦波，为提高电压的幅值还要经过放大电路进行放大，再通过升压变压器使 最后的输出电压的有效值在23V63V之间。通过检波电路得到直流电压，AD采集首先 将模拟信号转变成数字信号后，再将采集到的电压值送到单片机中，最后通过单片机送 到数码管显示电压，为保证放大电路中TDA7294的正常工作，单片机控制系统还通过稳 压电路为其提供电压。中频电源设计原理流程图如图3-1所示。振荡电路

8、-分频电路-积分电路-放大电路图3-1 400Hz中频电源设讣原理流程振荡电路为得到频率稳定性很高的振荡信号，多采用山石英晶体组成的石英晶体振荡器。石 英晶体的电路符号及振荡电路如图3-2所示。百度文库让每个人平等地捉升口我33在石英晶体两个管脚加交变电场时，它将会产有利于一定频率的机械变形，而这种 机械振动乂会产生交变电场，上述物理现象称为压电效应。一般情况下，无论是机械振 动的振幅，还是交变电场的振幅都非常小。但是，当交变电场的频率为某一特定值时， 振幅骤然增大，产生共振，称之为压电振荡。这一特定频率就是石英晶体的固有频率， 也称谐振频率。石英晶体的选频特性非常好，吊联谐振频率fs也极为稳

9、定，且等效品质因数Q值 很高。只有频率为fs的信号最容易通过，而其他频率的信号均会被晶体所衰减。电路中并联在两个反相器4069输入，输出间的电阻R的作用是使反相器工作在线 性放大区，R的阻值分别为和。电容G用于两个反相器间的耦合，而C：的作用，则是抑 制高次谐波，以保证稳定的频率输出。电容C：的选择应使2nRC:fsl,从而使RC,并联 网络在fs处产生极点，以减少谐振信号损失。G的选择应使G在频率为fs时的容抗可 以忽略不计。电路的振荡频率仅取决于石英晶体的吊联谐振频率fs,而与电路中的R, C的数值 无关。这是因为电路对fs频率所形成正反馈最强而易于维持振荡。为了改善输出波形，增强带负载的

10、能力，通常在振荡器的输出端再加一级反相器4069o输入的信号为4MHz,这样输岀的信号频率为4MHz。分频电路CD4024分频器然后进入CD4024分频器用。CD4024是多位二进制输出串行计数器，它是7位的串 行计数或分配器。如图3-3所示。图3-3 CD4024分频器是山D型触发器组成的二进制计数器。多位二进制计数器主要用于分频和定时，使 用极其简单和方便。CD4024特点是IC内部有7个计数级，每个计数级均有输出端子，即Q1Q7CD4024计数工作时，Q1是CP脉冲的二分频；Q2乂是Q1输出的二分频；Q3乂是Q2输出的二分 频所以有fQ7 = f3CPo所以进入CD4024的信号4096

11、KHZ在Q1端输出的信号为2048KHz,在Q2端输出的信402421 1 2 2 3 3 4 4 5 5心7 7 Q Q QQQQQQQQQQQQR4百度文邮-让每个人平等地捉升口我44号为1024KHZ,在Q3端输出的信号为512KHz,在Q4端输出的信号为256KHz,在Q5端 输出的信号为128KHz,在Q6端输出的信号为64KHz,在Q7端输出的信号为32KHz。 然 后32KHz的信号乂进入一个CD4024分频器，在第二个分频器的Q1端的输出信号为16KHz,在Q2端的输出信号为8KHz,在Q3端的输出信号为4KHz。这样输出频率为4KHz的信号乂进入下一个分频器74LS90。74

12、LS90计数器74LS90是异步十进制计数器旧。其逻辑电路图和引脚图如图34所示。它由1个1位二进制计数器和1个异步五进制计数器组成。 如果计数脉冲由CLKO端输入，输出山Q0端引出，即得二进制计数器；如果计数脉冲由CLK1端输入，输出由Q1Q3引出，即是五进制计数器；如果将Q0与CLK1相连，计数脉冲山CLKO输入，输 出由Q0Q1引出，即得8421码十进制计数器。因此 乂称此电路为二一五一十进制计 数器。图3-4 74LS90计数器管脚图本设计中信号由CLK1端输入，输出由Q1Q3引出，即是五进制计数器。也可看成 五分频器，即Q3是CLK1输出的五分频，Q2是Q3输出的五分频4KHz信号输

13、入在Q3端输出是800Hz信号。此点输出波形为脉冲波形。输出为800Hz的信号乂进入下一个分频器一D触发器。D触发器边沿型D触发器如图3 5所示。百度文邮-让每个人平等地捉升口我55图3 5 D触发器边沿型触发器的特点是， 输出状态发生变化的时刻只能在时钟脉冲CP的上升沿触 发。输出状态Qn+1的值仅仅取决于Qn及CP信号有效沿时刻的输入信号，具备这种特点的 触发器就叫做边沿型触发器。D触发器是一种延迟型触发器，不管触发器的现态是0还是1, CP脉冲上升沿到来 后，触发器的状态都将改变成与CP脉冲上升沿到来时的D端输入值相同，相当于将数 据D存入了D触发器中。表3-1是边沿型D触发器的功能表。

14、表3-1边沿型D触发器DQnQn+1说明000输出状态与D端010状态相同101111从功能表写出D触发器的特性方程为:Qn + = D()D触发器为二分频触发器。即从Q输出的信号为400Hz的方波。400Hz方波要进行二次积分，整形变成正弦波。积分电路方波变三角波电路如图3-6 (a)所示。由图可见，在理想条件下，RF-100kcII10u图3 6 (a )基本积分电路(/) _(Rdt如果电容两端的初始电压为零，则1Uo(t) =-jUidtRC 百度文库让每个人平等地捉升口我66当L(t)是幅值为E：的阶跃电压时1丨1Uo=-fUidt =-EitCTQCT此时，输出电压U(t)随时间线

15、性下降，如(3-3)可知，时间常数RC的数值越大,达到给定的U。值所需要的时间越长。当Ui(t)是峰值振幅为Us的方波时,u(t)的波形则为三角形波，如图3-6 (c)所 示。这时，根据式()，输出电压的峰一峰值为在实际的积分电路中，通常都在积分电容C的两端并接反馈电阻&如图3-6(a)所示。&的作用是产生直流负反馈，目的是减小集成运放输出端的直流漂移。但是，Rf的存在将影响积分器的线性积分关系，这时，输出积分波形将如图3-6 (b)虚线所示。 因此，为了改善积分器的线性度，&值取大些，但太大对抑制直流漂移不利，因此，& 应取适中的数值。三角波变正弦波如图3-7

16、所示。经过二次积分所得到的波形是正弦波， 但此时正弦波是带有直流的波形， 频率 是400Hzo经过整形滤出直流波形变成正弦波。Uip _ p RCIUop一p =T2八FiAUoR4,（10）脚比（9）脚后升到高电位，而关机时先变为低电位，这就使待机和关机过程均在静音状 态下进行，保证了放大器开关机无噪声。百度文邮-让每个人平等地捉升口我1010图3-11TDA7294标准应用电路信号经Cl、R1输入IC正相输入端脚。R7和IC第脚的R3、C3、C4构成负反 馈网络，本放大器的闭环增益约34倍。(9)、(10)脚分别是待机、静音端，由于第(10)脚R、C网络时间常数比第脚大， 使得开关机均在静

17、音下进行， 避免了开关冲击声，C7为自 举电容。通过TDA7294放大后输出信号频率仍为400Hz,电压的幅值在4OV左右。然后通过升压变压器，变压比为1：4,得到的电压幅值为170V左右，则有效值在65V左右。经过检波电路后，得到直流电压，有效值在25V63V之间，频率仍为400Hz。4电子控制单元电路4.控制电路的原理与设计方案 电源供给模块(1) 4-VI和-VI的电源如图4一3所示。OUT22K百度文邮-让每个人平等地捉升口我1111图4一3 + VI和-VI供电模块+V1和-VI分别提供+30V和-30V电压供给TDA7294所用。1继电器的定义继电器是一种当输入量（电、磁、声、光、

18、热）达到一定值时，输出量将发生跳跃 式变化的自动控制器件。继电器也是一种电门，但与一般开关不同，继电器并 非以机械方式控制的，它是以一定的输入信号（如电流、电压或其它热、光非电信号）实 现自动切换电路的“开关”。所以，它是一种自动电器元件。2继电器的分类继电器的分类方法较多，可以按作用原理、外形尺寸、保护特征、触点负载、产品 用途等分类。按作用原理分为：电磁继电器（在输入电路内电流的作用下，山机械部件的相对运动产生预定响应的 一种继电器）。固态继电器（输入、输出功能山电子元件完成而无机械运动部件的一种继电器）。 时间继电器、温度继电器等。3继电器工作原理本设计中是一款，是一种由固态电子组件组成

19、的新型无触点开关，利用开关三极管 的开关特性，达到无触点、无火花、而能接通和断开电路的口的，控制信号通过三极管 使发光二极管发光，光源促使与继电器相连的三极管导通，电能转换为磁能，从而使继 电器开关闭合，这样就可以输出VI电压。（2）V3和V5的电源如图4一4所示。+9VU14T+5V13TC38a NO-*C4IOUFr=-c1(百度文库让每个人平等地捉升口我1212图4一4 V3和V5供电模块V3和V5通过芯片7805分别提供+5V电圧。 V2和V4的电源如图4一5所示。30 VLK13I7+9VR415OK图4 5 V2和V4供电模块V2和V4通过芯片LM317分别提供+9V电压。5测试

20、结果(1)分步调试过程测量值如下表表5-1测量值电路波形频率测试电压振荡电路正弦波4MHz分频电路CD1024分频方波IKHz74LS90分频脉冲波形800HzD触发器方波100Hz积分电路正弦波400Hz放大电路负反馈放大正弦波400HzTDA7294放大正弦波400Hz升压变压器正弦波400Hz检波电路正弦波400Hz60V(有效值)调试过程中， 振荡电路岀来的频率是十分稳定的， 因为本设计要求的频率稳定性特 别高，所以一定要通过石英晶体振荡电路给整个电路一个稳定的信号。分频电路中因为CD4024是山D触发器构成的，所以出来的波形是方波。经过积分电路以后，正弦波是带 有直流的，要通过整形，

21、变成正弦波。在TDA7294放大之前，电压的幅值都是不够大的, 所以要经过TDA7294放大，放大倍数很大，由图表可以看出。(2)输出结果的测量试验的结果通过对旋转变圧器输出电压的测量，结果符合要求。旋转变压器可以改变的最大变压比为，如输入为10V的电压，最大输出电压为。本百度文库让每个人平等地捉升口我1414参考文献1曹汉房，陈耀奎.数字技术教程，北京：电子工业出版社，1995年2635.2康华光， 邹寿彬.电子技术基础 （数字部分） ， 北京： 高等教育出版社，2003年，253259.3李士雄，丁康源.数字集成电子技术教程，北京：高等教育出版社，1993年，63 70.4康华光， 陈大钦

22、.电子技术基础 （模拟部分） ， 北京： 高等教育出版社，2003年,333335.5衣承斌， 刘京南编.模拟集成电子技术基础。 南京： 东南大学出版社， 1994年,102115.6童诗口主编.模拟电子技术基础，北京：高等教育出版社，1998年，70-78.7李广弟，朱月秀，王秀山.单片机基础（修订版），北京：北京航空航天大学出 版社，2001年，1617.8刘瑞新，赵全利，赵建军等.单片机原理及应用教程，北京：机械工业出版社，2003年7月，157164.9梅丽凤，王艳秋，张军等.单片机原理及接口技术，北京：北京交通大学出版社,2004年,296303.10楼然苗，李光飞.51系列单片机设

23、计实例，北京：北京航空航天大学出版社，2002年，49一52.11吴金戌，沈庆阳，郭庭吉.8051单片机实践与应用，北京：清华大学出版社，2001年，293300.12秦玲，刘敬波.一种用于D/A转换电路的带隙基准电压源的设计，电子设计应 用，2006年5月,100112.13 Low power DCVSL circuits employing AC power supply WU Xunwei,HANG Guoqiang,Massoud Pedram .14 Maksimovic, D., Oklobdzija, V. C., Nikolic, B. et al., Clocked CMO

24、S adiabatic logic withintegrated single-phase power-clock supply: experimental results, in Proc, of the InternationalSymposium on Low-Power Electronics and Design, Monterey, New York: IEEE, 1997,323327.15 Wu, X., Pedram, Low power CMOS circuits with alternative power supply, in Proc. ChinaEleventhCo

25、nference on Integrated Circuitsand Silicon Materials （in Chinese） , 1999, 688691.百度文库让每个人平等地捉升口我1515L16JWu,X,Hang, G, Energy recovery circuits with cross coupled structure, J of Circuits andS ystems (in Chinese), 2000, 5(2), 1一8.致谢转瞬之间大学三年的生活已经接近尾声，从上学期毕业设汁题目的选择到现在顺利 的完成，在此过程中我非常感谢我的指导老师李杰老师，他们给予了我极

26、大的帮助与支 持使我受益匪浅。在不久的儿个月，我也要踏上工作岗位，老师们那种踏实勤恳、一丝 不苟、认真求实的优良品质和学习作风是值得我去学习和发扬的。毕业设计是对我大学三年学习的总结和概括，基本融会了我所学到的知识，在本课 题的研究上，虽然我遇到很多麻烦和困难，但是李杰老师给予了我很大支持和鼓励。从 最初的实物制作到程序的编写，一遍一遍的重复调试，使我深深的感受到在任何时候都 不要轻言放弃，做人如此，做事亦如此。设计过程加深了我对所学知识的掌握，同时也 接触到不少新的知识，既增长了见识，又开阔了眼界。最后我要对我的老师们说一句老师您辛苦了，衷心的谢谢您！附录系统电路图r2.J orcJ_ii/

27、JP2JPIIIESW.R ?AIi DPYS.dp百度文库让每个人平等地捉升口我1616英文资料及中文翻译FLIP-FLOPS1IntorduceIn this passage, we show how to design flip-flops, which operate as one-bit memory cells.Flip-flops are also called latches. Logic circuits constructed using flip-flops can have the presentoutput be a function of both the past

28、 and present inputs Such circuits are called senfiential logiccircuitsAll flip-flops are based on the same principle: Positive feedback is used to produce a circuitthat is bistable . A bistable circuit is one that has two stable operating points. Which operatingpoint the circuit is in is called the

29、state of the circuit. If the state can be sensed and changed, thenthe circuit can function as a one-bit memory element.The simplest bistable circuit is constructed using two inverters in a loop as shown in Figure 1 circuit only has two nodes, A and B Because of die inverters, if A is high, B must be

30、 lowand vice versa; hence, the circuit has two stable statesThe operation of the bistable circuit can also be viewed using a plot of the transfercharacteristic of the two inverters in series, as shown in Figure 1 2 Part (a) of the figureshows the static transfer characteristic of one of the inverter

31、s. When the input voltage is belowthe threshold (a logical ZERO), the output voltage is high (a logical ONE). When the inputvoltage is greater than the threshold, the output voltage is low. In part (b) of the figure, we showthe transfer characteristic that results from putting both inverters in seri

32、es. Any solution of theequations for this circuit must also lie on this characteristic. Because of the external connection,the input and output voltages of the series connection of the two inverters must be the same Therefore, we draw a line with a slope of unity on the plot as well. This line is ca

33、lled the load line,because it represents the external load connection for the two inverters in series Any solution ofthe equations for this circuit must also lie on the load line. Therefore, when the equations aresimultaneously solved, the only possible operating points are found where the straight

34、lineintersects the transfer characteristic. There are three intersections on the plot, but only two ofthem are stable, as we will now demonstrate.The point where the load line intersects the middle of the transfer characteristic is not stable.To see that this statement is true, suppose for the momen

35、t that the circuit is at this point. If theinput voltage increases at all (due to noise or some change in the circuit), the output voltage ofthe inverters must also increase But the output is input, so as it increases, it causes furtherincreases in the output, and the original change is magnified. T

36、his positive feedback will quickly百度文库让每个人平等地捉升口我1617drive the circuit to the top operating point shown. At that point, the input and百度文库让每个人平等地捉升口我1717output of the two-inverter chain are high and the midpoint (VBin Figure 1 1) is low, so thecircuit is stable and can remain in this state forever. I

37、f we started at the midpoint and let the inputvoltage decrease a bit, we would end up at the lower operating point, which is again stable.In the sections that follow, we show how we can move this bistable circuit from oneoperating point to the other. The internal positive feedback will then hold the

38、 circuit at that stateuntil we deliberately change it; hence, the circuit has memory.(a)Figure 1 2 (a) One inverter and its transfer characteristic(b) The transfer characteristic for two inverters in series and the load line for the circuit2 The Set-Reset Flip-FlopA set-reset (SR) flip-flop is shown

39、 in Figure 2 1(a). A table describing the function ofthe circuit is shown in part (b) of the figure, and the schematic symbol is shown in part (c). Thisfunction table is similar to a truth table, but it describes a dynamic situation, not a static百度文库让每个人平等地捉升口我one. The output is the output at some d

40、iscrete time, denoted by Qn, and the table includes anentry for the previous state of the flip-flop (Qn-i)- Although the circuit is drawn differently, thetwo NOR gates are in series, just like the inverters in Figure 12(b). The configuration shownhere is usually described as cross coupled The flip-f

41、lop has two outputs that are complementsof each other. We usually consider the Q output to be the state of the flip-flop sRQ=00Ort01010111不允许的(b)(C)Figure 2 1 (a) An SR flip-flop,(b) a table describing the circuits function(c) the schematic symbol.The circuit operates in the following way: If both i

42、nputs (S and R) are zero, the previousstate is retained Suppose, for example, that Qn-i is high ,ONE). Then the output of the bottomNOR, whichis(?n-i , will be low，ZERO), independently of what S is. In thiscase, both inputsto the top NOR are low, so its output is high, as originally assumed. Now sup

43、pose that Qn-i islow. In this case, both inputs to the bottom NOR are low, soQis high. Therefore, the output ofthe top NOR, Qn.u will be low, as assumed Now consider what happens when the set input, S, goes high while R remains low. The outputof the bottom NOR,Qi, will now go low, independent of wha

44、t the previous state of百度文库让每个人平等地捉升口我1818the circuit was. With R low as welt this guarantees that Qnwill go high , the flip-flop hasbeen set). Note that S does not have to stay high. Once the flip-flop is set, the S input can golow again, and the state will be retained. This sequence of events is i

45、llustrated in Figure 2 2The figure shows that there is some delay through each gate, so it takes a time tj for the change atthe gate input to affect its output.Figure 22 A timing diagram for the SR flip-flop. The arrows indicatewhich transition causes the following changeThe operation of the reset i

46、nput is similar. If R goes high while S is kept low, the output ofthe top NOR, Qn, will go low the flip-flop is “reset”). With Qnand S both low, the bottom NORoutput will be high The reset input can go low again, and this new state will be retained. Thissequence is also illustrated in Figure 2 2 Fin

47、ally, we note that both inputs should not be allowed to go high at the same time. If thishappens, both NOR outputs go low, so Q andQare not complements anymore. Also, if bothinputs are high and then go low at exactly the same time, we cant predict what the resultingoutput state will be, since both o

48、utputs will try to go high, which is a condition that cannot besustained Which output will actually stay high depends on mismatches in the NOR gates andcannot be predicted 3 The JK Flip-FlopThe fact that the output of an SR flip-flop is undefined if both inputs go high is troublesomein many applicat

49、ions The JK flip-flop avoids什“s problemand is more flexible initsoperation.The JK flip-flop is a clocked flip-flop; that is, it requires a separate clock input to operate Thisclock signal is usually a square wave with a fixed period Logic circuits that require a clock andthat only allow output trans

50、itions to occur in synchrony with the clock are calledsynchronous-logic circuits The clock can be generated using an astable multivibrator.1919百度文库让每个人平等地捉升口我2020(a)iQ -CKQ-(b)JKQa00Qs-i01010111e-(c)Figure 3 1 (a) A JK flip-flop made using an SR flip-flop. (b) The Schematicsymbol for a JK flip-flop

51、(c) the function table (The flip-floponly changes state when the clock is high.)A JK flip-flop is shown in Figure 31(a); the schematic symbol is shown in part (b) of thefigure, and the function table is shown in part (c) The AND gates serve to enable the inputs tothe SR flip-flop That is, only when

52、the clock is high are the J and K inputs able to affect the SRflip-flop. In addition to needing the clock to be high, the J input affects S only if the SR flip-flopis currently reset, and the K input affects R only if the flip-flop is currently set. Therefore, we seethat when both J and K are low, S

53、 and R will be low, and the flip-flop will hold its present statejust like the SR flip-flop. When J is high and the flip-flop is currently reset , Qn i is high), theflip-flop will be set when the clock goes high, independently of what K is. If K is high and theflip-flop is currently set Qn-i is high

54、), the flip-flop will reset when the clock goes high,independently of what J is. It follows that if both J and K are high, the flip-flop will toggle itsstate when the clock goes high. When operated in the toggle mode,QQ百度文库让每个人平等地捉升口我a JK flip-flop is sometimes called a T flip-flop The JK flip-flop

55、as shown in Figure 3 1 has a major problem: It will work only if theclock pulse width，the time the clock is high) is short compared with the propagation delay ofthe gate To understand this limitation, consider what happens when J and K are both high andQn-i is low. In this case, the output of the fl

56、ip-flop will toggle when the clock goes high, asindicated in the function table. But, if the output toggles and the clock is still high, the outputwill toggle again This process will repeat until either the clock goes low or J or K changes Inorder to avoid this problem, we use master-slave JK flip-f

57、lop A master-slave JK flip-flop is shown in Figure 3 2 The master flip-flop is enabledwhen the clock is high, so the data are latched into the master during that portion of the clockcycle During that time, c is low and the slave is disabled and holds the previous value Thenthe clock goes low, c goes

58、 high and enables the slave The data from the master are thentransferred to the slave and show up at the output. Since the master and slave flip-flops are neverenabled at the same time, the output will not continue to toggle if the clock is held in any onestate for too long The clock does have to re

59、main in each state long enough to allow for thepropagation delay through one of the flip-flops.c-*-Figure 3 2 A master-slave JK flip-flopIn designing a master-slave JK flip-flop, we must carefully consider the propagation delays ofthe individual gates to prevent the slave from changing before it sho

60、uld For example, in thefigure, the data on SMand RMcan change one gate delay after the clock goes high The slaveclock, which is c, goes low one inverter delay after the clock goes high We must be sure thatthe slave clock changes before the output of the master flip-flop can change; otherwise, the datawill pass on