VHDL洗衣机设计

1、EDA 课程实训报告、实训课题：洗衣机控制器的设计、设计的内容及要求：1设计一个洗衣机控制器，要求为：1)洗衣机控制器可以驱动洗衣机进行洗涤、漂洗或烘干；2)3)4)可以暂停或停止洗衣机工作；洗衣机控制器可以设置洗衣机的工作时间，工作时间最短 1 分钟，最长 30 分钟，在工 作过程中，工作时间以倒计时显示，若时间为 0 洗衣机停止工作； 洗衣机在待机状态时，洗衣机控制器可以设置洗衣机的工作方式和工作时间；5)6)利用四个数码管显示洗衣机待机时的设置时间和工作时的运行时间，利用一位数码管 显示洗衣机待机时所设置的工作方式运行时的工作方式； 利用三个 LED 分别表示驱动洗衣机进行洗涤、漂洗或烘

2、干。2洗衣机控制器可以划分为状态机模块、 计时器模块、设置模块和显示选择模块。 在 QuartusII中输入各个模块的代码，编译综合，仿真，完成各个模块的软件设计；4把各个模块组合起来，综合编译，仿真，完成整个交通灯控制器系统的软件设计；5. 选择电路方案锁定管脚，把程序下载到实验箱中，利用实验箱进行硬件实现；6. 完成实训报告。实训报告包括：1) 设计的任务和要求；2) 模块的划分和系统总框图；3)各个模块的实现，包括模块的作用，模块的输入与输出情况，模块状态图，模块的代码以及注释，模块的波形图;4)系统的实现，包括系统总原理图，系统的波形图;5)管脚的锁定关系;状态切换 >>&

3、gt; 有限状态机 按定时时间及时 >>> 定时计数器 显示时间>»数码管译码驱动器 接收设置时间 >>> 时间设置键盘扫描器 接收设置模式 >>> 模式设置键盘扫描器 切换显示运行时间和设置时间 >>> 二路选择器 切换显示运行模式和设置模式 >>> 二路选择器整体设计示意图:四.系统组成以及系统各部分的设计:1. 状态机的设计:状态机要完成的功能:能设置工作模式;控制洗涤、漂洗、干衣的驱动输出;能启动、暂停、停止洗衣机控制器;能重启、暂停和停止定时器;能接收定时器的到时标志;能使能键盘

4、扫描计数器;能控制二路选择器。状态图分析设计如下:干衣(dry)待机（嚴dy）时间至漂洗（iwE）Slv(wait)模块设计图如下:niodeinI20TOttec 肉20CLKwoul2.0pausekenstart5Glstoptentcin:stop/WASHMACHN-enr-Jri状态机仿真图如下:10V ALX2JiJnnnnnnrnIJJ11 OJ A53fiyTTiJ13：Jt .D；-SmA1Ln11 1fu111L_Ji '1L.aaEI.LLL1.,aJ:匸d.厶J_ JJ.-,K 口sU rni p wl7J Bl :（Nlt el ecfa JGOi.p L：

5、 2幼.卩 235（坤 30）,0 1.14监0 皿 血卩 阪卩 a GM.p lu Cf（卩 a 珈.0d 5E5 K ''r JirLruuunnrjuuLrLTTrLrrjwuuWnnjWuuWLTTjirjuuuvmrjWLr2.定时器设计:定时器的功能:能通过使能端暂停和允许定时器工作;能停止并复位定时器;能进行定时;能输出定时标志模块设计图如下:H ! dingshictkcintenomg3.0tstop03g3,.0'iriis3 0oms3,.0issE3.Ooss3 01'imgP-.Ousg3.Oi inst定时器波形图如下:Yiip三EO

6、.D 3516C 0 ZE £40.1 Bs 330.0 ns1 1MMlO 口1叫nz 叫心吨g现匹SOC-Ohs 叫蓝羽“Tsue199 迓 T.E竺dkjimoiwjLTTLmAWnnnnLOJwnmnmLmiowLnnmw:tn.1111 1皿?1! 1Q ms1： 1 1 !B氓L，2!启130: 1 :Q瞬：.丨1 .!B nsA；n X1ti ''''!冠23QR:划i劇zzczL1:趣Q nsi1 ：0 XI-侗i51. W【町.I：3:B «s6:：0 X血率醱阳腕ffilE®!磁e魄豳E便SIS邵迴豳豳EEIEE

7、®043cm,1113. 时间设置:时间设置键盘扫描器的功能:能响应按键;能在使能端的控制下工作模式设计图如下:叶Pkeykinkeniinns3.Oiss3.,0 iimg3,.Oisg3.0i inst 1口.波形图如下:br SOOiG 1611心 如：归魏.0临aOnE 呃卫 5M.0ii£ 随0丄 -30% 聊.仏 珈丄 9&10血_ LL!_i_!i:!：_血饥込QSJteniwirmrr伽rLRnnnnmiiiwrnmwiMrmrLKnMm"lO0fel?3i4. 模式设置:模式设置键盘扫描器的功能:预设工作模式，” 000 ”为待机，” 0

8、01 ”为洗涤，” 010”为漂洗，” 022 ”为干衣，” 100”为暂停模式设计图如下:'mcde“'"皿巴占Lkinmodeset2.0kenLED2.Oinst；1口.r波形图如下:Mile St,Pit 310tis leODii罠）厉5逍旳 fSEnz狀厲涮w训.hs刑临跚血 BO:s观血M Sf.tS 口1JLto哼Ihl3®尋& 0诚熾J-nrnonAMnjinnLnRnRnjwwLnTLfwuwLnIIII I5. 二路选择器二路选择器的功能:设置显示运行时间还是设置时间，显示运行模式还是设置模式。模式设计图如下:fn5dis1Da

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15、电路结构图NO.7附录代码:1.状态机LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY SHELL WASHMACHINE ISPORT (CLK,modeinO,modein1,modein2 ,p ause,start,st op ,tcin: IN std_logic;ken,modeout0,modeout1,modeout2,sel,ten,tst op, wout0,wout1,wout2 : OUTstd_logic);END;ARCHITECTURE BEHAVIOR OF SHELL WASHMACHINE ISTYPE typ

16、e_sreg IS (dry,ready,rinse,wait up ,wash);SIGNAL sreg, next_sreg : ty pe_sreg;SIGNAL next_ken,next_modeout0,next_modeout1,next_modeout2,next_sel,next_ten.next tstop,next wout0,next wout1,next wout2 : std logic;SIGNAL modeout : std_logic_vector (2 DOWNTO 0);SIGNAL wout : std_logic_vector (2 DOWNTO 0)

17、;BEGINPROCESS (CLK, stop, next_sreg, next_ken, next_sel, next_ten, next_tstop,next_modeout2, next_modeout1, next_modeout0, next_wout2, next_wout1,next_wout0)BEGINIF ( stop='1' ) THENsreg <= ready;sel <= '0'ken <= '1'ten <= '1'tstop <= '1'modeout

18、2 <= '0'modeout1 <= '0'modeout0 <= '0'wout2 <= '0'wout1 <= '0'wout0 <= '0'ELSIF CLK='1' AND CLK'event THENsreg <= next_sreg;ken <= next_ken;sel <= next_sel;ten <= next_ten;tstop <= next_tstop;modeout2 <=

19、next_modeout2;modeout1 <= next_modeout1;modeout0 <= next_modeout0;wout2 <= next_wout2;wout1 <= next_wout1;wout0 <= next_wout0;END IF;END PROCESS;PROCESS (sreg,modein0,modein1,modein2,pause,start,tcin,modeout,wout)BEGINnext_ken <= '0' next_modeout0 <= '0' next_mod

20、eout1 <= '0' next_modeout2<= '0' next_sel <= '0' next_ten <= '0' next_tstop <= '0' next_wout0 <= '0' next_wout1 <= '0' next_wout2 <= '0'CASE sreg ISmodeout<=std_logic_vector'("000"); wout<=std

21、_logic_vector'("000");next_sreg<=dry;WHEN dry =>IF ( pause='0' AND tcin='0' ) THENnext_sreg<=dry;next_ten<='1'next_tstop<='0'next_ken<='0'next_sel<='1'modeout <= (std_logic_vector'("011");wout <= (

22、std_logic_vector'("100");END IF;IF ( tcin='0' AND pause='1' ) THENnext_sreg<=waitup;next_ten<='0'next_tstop<='0'next_ken<='0'next_sel<='1'modeout <= (std_logic_vector'("100");wout <= (std_logic_vector

23、9;("000");END IF;IF ( tcin='1' ) THENnext_sreg<=ready;next_ten<='1'next_tstop<='1'next_ken<='1'next_sel<='0'modeout <= (std_logic_vector'("000");wout <= (std_logic_vector'("000");END IF;WHEN ready =>

24、;IF ( modein1='0' AND modein0='0' ) OR ( modein2='1' ) OR ( start='0' )THEN next_sreg<=ready;next_ten<='1'next_tstop<='1'next_ken<='1'wout <= (std_logic_vector'("000");END IF;IF ( modein0='1' AND modein1=

25、9;1' AND modein2='0' AND start='1' ) THENnext_sel<='0'modeout <= (std_logic_vector'("000");next_sreg<=dry;next_ten<='1'next_tstop<='0'next_ken<='0'next_sel<='1'modeout <= (std_logic_vector'("01

26、1"); wout <= (std_logic_vector'("100");END IF;IF ( modein0='0' AND modein1='1' AND modein2='0' AND start='1' ) THENnext_sreg<=rinse;next_ten<='1'next_tstop<='0'next_ken<='0'next_sel<='1'modeout <=

27、 (std_logic_vector'("010"); wout <= (std_logic_vector'("010");END IF;IF ( modein0='1' AND modein1='0' AND modein2='0' AND start='1' ) THENnext_sreg<=wash;next_ten<='1'next_tstop<='0'next_ken<='0'next_s

28、el<='1'modeout <= (std_logic_vector'("001");wout <= (std_logic_vector'("001");END IF;WHEN rinse =>IF ( pause='0' AND tcin='0' ) THENnext_sreg<=rinse;next_ten<='1'next_tstop<='0'next_ken<='0'next_sel&l

29、t;='1'modeout <= (std_logic_vector'("010");END IF;IF ( tcin='0' AND pause='1' ) THENnext_tstop<='0'wout <= (std_logic_vector'("010");next_sreg<=waitup;next_ten<='0'next_ken<='0'next_sel<='1'modeo

30、ut <= (std_logic_vector'("100"); wout <= (std_logic_vector'("000");END IF;IF ( tcin='1' ) THEN next_sreg<=ready;next_ten<='1'next_tstop<='1'next_ken<='1'next_sel<='0'modeout <= (std_logic_vector'("00

31、0"); wout <= (std_logic_vector'("000");END IF;WHEN waitup =>IF ( modein1='0' AND modein0='0' ) OR ( modein2='1' ) OR ( pause='1' )THEN next_sreg<=waitup;next_ten<='0'next_tstop<='0'next_ken<='0'next_sel<=

32、'1'modeout <= (std_logic_vector'("100");wout <= (std_logic_vector'("000");END IF;IF ( modein0='1' AND modein1='1' AND modein2='0' AND pause='0' ) THENnext_sreg<=dry;next_ten<='1'next_tstop<='0'next_ken

33、<='0'next_sel<='1'modeout <= (std_logic_vector'("011");wout <= (std_logic_vector'("100");END IF;IF ( modein0='0' AND modein1='1' AND modein2='0' AND pause='0' ) THENnext_tstop<='0'next_sel<='1&#

34、39;next_sreg<=rinse;next_ten<='1'next_ken<='0'modeout <= (std_logic_vector'("010");wout <= (std_logic_vector'("010");END IF;IF ( modein0='1' AND modein1='0' AND modein2='0' AND pause='0' ) THENnext_sreg<=wa

35、sh;next_ten<='1' next_tstop<='0'next_ken<='0'next_sel<='1'modeout <= (std_logic_vector'("001");wout <= (std_logic_vector'("001");END IF;WHEN wash =>IF ( pause='0' AND tcin='0' ) THENnext_sreg<=wash;ne

36、xt_ten<='1'next_tstop<='0'next_ken<='0'next_sel<='1'modeout <= (std_logic_vector'("001");wout <= (std_logic_vector'("001");END IF;IF ( tcin='0' AND pause='1' ) THENnext_sreg<=waitup;next_ten<='0&#

37、39;next_tstop<='0'next_ken<='0'next_sel<='1'modeout <= (std_logic_vector'("100");wout <= (std_logic_vector'("000");END IF;IF ( tcin='1' ) THENnext_sreg<=ready;next_ten<='1'next_tstop<='1'modeout <=

38、 (std_logic_vector'("000");wout <= (std_logic_vector'("000");next_ken<='1'next_sel<='0'END IF;WHEN OTHERS =>END CASE;next_modeout2 <= modeout(2);next_modeout1 <= modeout(1);next_modeout0 <= modeout(0); next_wout2 <= wout(2);next_wou

39、t1 <= wout(1);next_wout0 <= wout(0);END PROCESS;END BEHAVIOR;LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY WASHMACHINE ISPORT (modein : IN std_logic_vector (2 DOWNTO 0);modeout : OUT std_logic_vector (2 DOWNTO 0);wout : OUT std_logic_vector (2 DOWNTO 0);CLK,pause,start,stop,tcin: IN std_logi

40、c;ken,sel,ten,tstop : OUT std_logic);END;ARCHITECTURE BEHAVIOR OF WASHMACHINE ISCOMPONENT SHELL_WASHMACHINEPORT (CLK,modein0,modein1,modein2,pause,start,stop,tcin: IN std_logic;ken,modeout0,modeout1,modeout2,sel,ten,tstop,wout0,wout1,wout2 : OUTstd_logic);END COMPONENT;BEGINSHELL1_WASHMACHINE : SHEL

41、L_WASHMACHINE PORT MAP (CLK=>CLK,modein0=>modein(0),modein1=>modein(1),modein2=>modein(2),pause=>pause,start=>start,stop=>stop, tcin=>tcin,ken=>ken,modeout0=>modeout(0),modeout1=>modeout(1),modeout2=> modeout(2),sel=>sel,ten=>ten,tstop=>tstop,wout0=>wo

42、ut(0),wout1=>wout(1),wout2 =>wout(2);END BEHAVIOR;2定时器：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dingshi isport(clk,ten,tstop:in std_logic;ims:in std_logic_vector(3 downto 0);iss:in std_logic_vector(3 downto 0);img:in std_logic_vector(3 downto 0);isg:in st

43、d_logic_vector(3 downto 0);cin:out std_logic;omg, osg:buffer std_logic_vector(3 downto 0););oms:buffer std_logic_vector(3 downto 0); oss:buffer std_logic_vector(3 downto 0)end;architecture cml of dingshi is beginPROCESS(clk, ten, tstop)BEGINIF ten='1' THENIF tstop='1' THENosg<=isg

44、;ELSIF clk'EVENT AND clk='1' THENIF osg="0000" THENIF oss>"0000" OR omg>"0000" OR oms>"0000" THENosg<="1001"ELSEosg<="0000"END IF;ELSEosg<=osg-1;END IF;END IF;END IF;END PROCESS;PROCESS(clk, ten, tstop, osg)BEG

45、INIF ten='1' THENIF tstop='1' THENoss<=iss;ELSIF clk'EVENT AND clk='1' THENIF osg="0000" THENoss<="0101"IF oss=0 THENIF omg>"0000" OR oms>"0000" THENELSEoss<="0000"END IF;ELSEoss<=oss-1;END IF;END IF;END

46、IF;END IF;END PROCESS;PROCESS(clk, ten, tstop, osg, oss)BEGINIF ten='1' THENIF tstop='1' THENomg<=img;ELSIF clk'EVENT AND clk='1' THENIF oss=0 and osg=0 THENIF omg=0 THENIF oms>0 THENomg<="1001"ELSEomg<="0000"END IF;ELSEomg<=omg-1;END IF

47、;END IF;END IF;END IF;END PROCESS;PROCESS(clk, ten, tstop, osg, oss, omg)BEGINIF ten='1' THENIF tstop='1' THENoms<=ims;ELSIF clk'EVENT AND clk='1' THENIF omg=0 and osg=0 and oss=0 THENIF oms=0 THENoms<="0000"ELSEoms<=oms-1;END IF;END IF;END IF;END IF;EN

48、D PROCESS;PROCESS(clk, ten, tstop, osg, oss, omg, oms)BEGINIF ten='1' THENIF tstop='0' THENTHENIF clk'EVENT AND clk='1' THENIF oms=0 AND omg=0 AND oss=0 AND osg=1cin<='1'ELSEcin<='0'END IF;END IF;END IF;END IF;END PROCESS;END cml;3. 时间设置：library ieee

49、;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity key IS port( kin: in std_logic;ken: in std_logic;ims,iss,img,isg: buffer std_logic_vector(3 downto 0);end key;ARCHITECTURE cml OF key ISBEGINPROCESS(kin, ken)BEGINIF isg="1001" THENisg<=isg+1;END IF;END IF;END PROCESS;P

50、ROCESS(kin, ken, isg)BEGINIF ken='1' THENIF kin'EVENT AND kin='1' THENIF isg=9 THENIF iss="0101" THENiss<="0000"ELSEiss<=iss+1;END IF;END IF;END IF;END IF;END PROCESS;PROCESS(kin, ken, isg, iss)BEGINIF ken='1' THENIF kin'EVENT AND kin='1&

51、#39; THENIF iss="0101" AND isg="1001" THENIF img="1001" THENimg<="0000"ELSEimg<=img+1;END IF;END IF;END IF;END IF;END PROCESS;PROCESS(kin, ken, isg, iss, img)BEGINIF ken='1' THENIF img="1001" AND iss="0101" AND isg="1001" THENims<=ims+1;IF kin'EVENT AND kin='1' THENIF ims="0010" THENims<="0000"ELSEEND IF;END IF;END IF;END IF;END PROCESS;END cml;4. 模式设置：lib