一个牛人写的很快且不用状态机的动态RAM接口

1、一个牛人写的很快且不用状态机的动态RAM接口07f"constant RAS_REF_CODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1010"constant CAS_REF_CODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1110"constant WE_REF_CODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1011"constant WOR

2、KING_WR_CODE : std_logic_vector(working_shift_len-1 downto 0) := "00"&X"003"constant RAS_WR_CODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1011"constant CAS_WR_CODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1110"constant WE_WR_CODE : std_logi

3、c_vector(rcw_shift_len-1 downto 0) := "1110"constant DAT_WR_CODE : std_logic_vector(wt_shift_len-1 downto 0) := X"7f8"constant TRI_WR_CODE : std_logic_vector(wt_shift_len-1 downto 0) := X"c01"constant WORKING_RD_CODE : std_logic_vector(working_shift_len-1 downto 0) := &

4、quot;00"&X"001"constant RAS_RD_CODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1011"constant CAS_RD_CODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1110"constant WE_RD_CODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1111"constant DAT

5、_RD_CODE : std_logic_vector(rd_dat_shift_len-1 downto 0) := X"03f"&"11"constant WORKING_RFRS_CODE : std_logic_vector(working_shift_len-1 downto 0) := "00"&X"03f"constant RAS_RFRS_CODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1011"cons

6、tant CAS_RFRS_CODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1011"constant WE_RFRS_CODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1111"constant WORKING_PRE_CODE : std_logic_vector(working_shift_len-1 downto 0) := "00"&X"03f"constant RAS_PRE_C

7、ODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1011"constant CAS_PRE_CODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1111"constant WE_PRE_CODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1011"constant WORKING_LMR_CODE : std_logic_vector(working_shift_le

8、n-1 downto 0) := "00"&X"03f"constant RAS_LMR_CODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1011"constant CAS_LMR_CODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1011"constant WE_LMR_CODE : std_logic_vector(rcw_shift_len-1 downto 0) := "1

9、011"begin  ras_le_code <= (others => '0');  cas_le_code <= (others => '0');    wr_dat_code <= (others => '0');    wr_tri_code <= (others => '1');    rd_data_code <= (others => '0');

10、0;   if  rfrs = '1' then            working_code <= WORKING_RFRS_CODE;            ras_code <= RAS_RFRS_CODE;            cas_code <= CAS_RFRS_CODE;          &#

11、160; we_code <= WE_RFRS_CODE;    elsif  pre = '1' then            working_code <= WORKING_PRE_CODE;            ras_code <= RAS_PRE_CODE;            cas_code <= CAS_PRE_CODE;&#

12、160;           we_code <= WE_PRE_CODE;            ras_le_code <= RAS_LE_CMD_CODE;    elsif  lmr = '1' then            working_code <= WORKING_LMR_CODE;        

13、0;   ras_code <= RAS_LMR_CODE;            cas_code <= CAS_LMR_CODE;            we_code <= WE_LMR_CODE;            ras_le_code <= RAS_LE_CMD_CODE;    elsif  refr = '1' the

14、n            working_code <= WORKING_REF_CODE;            ras_code <= RAS_REF_CODE;            cas_code <= CAS_REF_CODE;            we_code <= WE_REF_CODE;   

15、 elsif  write = '1' then            working_code <= WORKING_WR_CODE;            ras_code <= RAS_WR_CODE;            cas_code <= CAS_WR_CODE;            we_cod

16、e <= WE_WR_CODE;            ras_le_code <= RAS_LE_CMD_CODE;            cas_le_code <= CAS_LE_CMD_CODE;            wr_dat_code <= DAT_WR_CODE;            wr_tri_code <

17、;= TRI_WR_CODE;    elsif  read = '1' then            working_code <= WORKING_RD_CODE;            ras_code <= RAS_RD_CODE;            cas_code <= CAS_RD_CODE;     

18、      we_code <= WE_RD_CODE;            ras_le_code <= RAS_LE_CMD_CODE;            cas_le_code <= CAS_LE_CMD_CODE;            rd_data_code <= DAT_RD_CODE;    else            working_code <= (others => '1');            ras_code <= (others => '1');            cas_code <= (others