用状态机实现ADC0809的采样电路的设计

1、用状态机实现ADC0809的采样电路的设计专业:电子信息科学与技术学号:200811526姓名:袁朝阳一实验目的:用状态机实现序列检测器的设计,了解一般状态机的设计和应用。二实验仪器:pc平台,Quartus II8.0软件,EDA6000实验箱。三实验原理:序列检测器可用于检测一组或多组由二进制代码组成的脉冲序列信号,当序列检测器连续收到一组串行二进制码后,如果这组码与检测器中预先设置的码相同,则输出1,否则输出0。四实验内容及操作步骤:1 对Quartus II8.0进行破解,操作步骤参考实验一。2创建工程:选择菜单File->New Preject Wizard命令,即弹出“工程设

2、置”对话框。设置后在编辑对话框中输入Vhdl代码如下:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY EX14 ISPORT (din : IN STD_LOGIC_VECTOR(7 DOWNTO 0; - IO55.IO48 (P13, P12, P10, P9 , P8 , P137, P136, P135clk : IN STD_LOGIC; - clock input for state - IO30(P125q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0; - IO15.IO08 (P64, P63, P62,

3、P60, P59, P51, P49, P48eoc : IN STD_LOGIC; - IO38(P116clock: OUT STD_LOGIC; - clock output for ADC0809 - IO39(P117start: OUT STD_LOGIC; - IO37(P114oe : OUT STD_LOGIC - IO34(P111;END EX14;ARCHITECTURE behv OF EX14 ISTYPE st_type IS (st0, st1, st2, st3, st4;SIGNAL lock: STD_LOGIC;SIGNAL current_state,

4、 next_state: st_type := st0;BEGINclock <= clk;PROCESS(clkBEGINIF clk'EVENT AND clk = '1' THENcurrent_state <= next_state;END IF;END PROCESS;PROCESS(lockBEGINIF lock'EVENT AND lock = '1' THENq <= din;END IF;END PROCESS;PROCESS(current_state, eocBEGINCASE current_state

5、 ISWHEN st0 =>start <= '0'oe <= '0'lock <= '0'next_state <= st1;WHEN st1 =>start <= '1'oe <= '0'lock <= '0'next_state <= st2;WHEN st2 =>start <= '0'oe <= '0'lock <= '0'IF eoc = '1

6、9; THENnext_state <= st3;ELSEnext_state <= st2;END IF;WHEN st3 =>start <= '0'oe <= '1'lock <= '0'next_state <= st4;WHEN st4 =>start <= '0'oe <= '1'lock <= '1'next_state <= st0;WHEN OTHERS =>start <= '0'

7、oe <= '0'lock <= '0'next_state <= st0;END CASE;END PROCESS;END behv;3 编译前对工程进行设置,然后对工程进行全程编译,编译结果如下: 采样电路的设计编译结果4波形仿真:打开波形编辑器,设置仿真时间区域,波形文件存盘,将工程的端口信号名选入波形编辑器中,编辑输入波形,仿真器参数设置,启动仿真器。仿真结果如下: 采样电路的设计波形仿真结果5查看电路图: 实验电路图6引脚设置和下载:选择Assignment 菜单中“Assignment Editor”项,在打开的编辑窗口中进行设置其结果如下: 引脚配置与下载打开编程窗和配置文件,设置编辑器,选择编辑器,最后单击下载标符Sta