教程原理实验

1、ADC结果显示analog voltsconverted valueRESULTx 3.0FFFh1111|1111|1111|00001.57FFh0111|1111|1111|00000.000731h0000|0000|0001|000000h0000|0000|0000|0000结果首先要右移4位600h为几伏？0x600 * 3 / 4095 1.12527 伏6ADC结果显示600h为 1.12527 伏 ，如何显示？0x600 * 3 / 4095 1.12527 伏即如何从600H得到：1，1，2，5，2，7 ？ 注意：int k; k=3 / 5; “k=?”62ADC结果显

2、示600h为 1.12527 伏 ，如何显示？0x600 * 3 / 4095 1.12527 伏计算过程：若A/D转换结果变量AD2中，AD2=0x600； 显示数组为XS（8），做以下运算：AD2 = AD2* 3 * 1000 / 4095 ；/ AD2 = 1125 XS(0) = AD2 / 1000 ；/ XS(0) =1XS(1) = xx;/ XS(1) =小数点XS(2) =(AD2%1000)/100 ；/ XS(2) = 1 XS(3) =(AD2%100)/10 ； / XS(3) = 263ADC_实验（1）u 硬件连接1. 只连接了ADC_B7引脚，（ADCINB7

3、）; ;2. 运放放大器为了阻抗匹配;3. 通过ADCB7调整ADC输入电压;4. ADCB7电压由可调电位器调节;6ADC输入引脚连接要将跳针J1位于1、2之间。65. . .ADC Module Block Diagram (Cascaded Mode) Analog MUXADCINA0Result MUXADCINA1ADCINA7ADCINB0 ADCINB1SOCEOCADCINB7Auto sequencerSoftwareEVA EVBExt Pin (ADCSOC)Start Sequence Trigger66CHSEL00 (state 0)CHSEL01 (state

4、1)CHSEL02 (state 2)CHSEL03 (state 3).CHSEL15 (state 15)MAX_CONV1RESULT15S/HBMUX BRESULT2S/HMUX12-bit A/D ConverterRESULT1RESULT0Result SelectS/HAMUX A. . . . .ADC Module Block Diagram (Dual-Sequencer mode) Analog MUXResult MUXADCINA0ADCINA1ADCINA7ADCINB0 ADCINB1SOC1/SOC2/ADCINB7EOC1EOC2SEQ1SEQ2Auto

5、sequencerAuto sequencerSoftwareSoftwareEVAEVBExt Pin(ADCSOC)Start SequenceStart Sequence TriggerTrigger67RESULT15CHSEL08 (state 8)CHSEL09 (state 9)CHSEL10 (state 10).CHSEL15 (state 15)CHSEL00 (state 0)CHSEL01 (state 1)CHSEL02 (state 2).CHSEL07 (state 7)MAX_CONV2MAX_CONV1RESULT9RESULT8Result SelectS/

6、HBMUX BRESULT7S/HMUX12-bit A/D ConverterSequencer ArbiterRESULT1S/HARESULT0Result SelectMUX AADC_实验（2）u ADC应用1. ADC上电：确定使用电平;2. ADC排序初始化：排序方式，启动方式等;3. ADC启动、等待、结果;4. 显示转换结果u 中断方式的应用1. 定时中断启动;2. 转换结束产生中断;u 编程：初始化寄存器；68Analog-to-Digital Converter RegistersRegisterAddressDescriptionADCTRL1ADCTRL20x0071

7、000x007101ADC Control Register 1ADC Control Register 2ADCMAXCONV ADCCHSELSEQ1 ADCCHSELSEQ2 ADCCHSELSEQ3 ADCCHSELSEQ4ADCASEQSR0x0071020x0071030x0071040x0071050x0071060x007107ADCum Conversion Channels RegisterADC Channel Select Sequencing Control Register 1ADC Channel Select Sequencing Control Registe

8、r 2ADC Channel Select Sequencing Control Register 3ADC Channel Select Sequencing Control Register 4ADC Auto sequence Status Register9ADCTRL30x007118ADC Control Register 3ADCST0x007119ADC Status and Flag RegisterADCRESULT00x007108ADC Conversion Result Buffer Register 0ADCRESULT10x007109ADC Conversion

9、 Result Buffer Register 1 ADCRESULT20x00710AADC Conversion Result Buffer Register 2: : :ADCRESULT140x007116ADC Conversion Result Buffer Register 14ADCRESULT150x007117ADC Conversion Result Buffer Register 15ADC_实验（3）上电程序void Adc_PowerUP()AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x3;/ADC带隙和参考电路加电for (i=0; i<

10、;1000000; i+)/至少5ms延时AdcRegs.ADCTRL3.bit.ADCPWDN = 1;/ADC核模拟电路加电for (i=0; i<10000; i+)/至少20us延时60ADC Control Register 3ADCTRL3 0x007118ADC ReferenceADC BandgapADC Power Down Power DownPower Down(except Bandgap & Ref.) 0 = powered down0 = powered down0 = powered down1 = powered up1 = powered u

11、p1 = powered up15 - 876543210ADC Clock PrescaleSampling Mode Select0 = sequential sampling mode1 = simultaneous sampling mode6ADCCLKPS3ADCCLKPS2ADCCLKPS1ADCCLKPS0SMODE_SELADCRFDNADCBGNDADCPWDNADC_实验（4）void Adc_Init()AdcRegs.ADCTRL1.bit.SEQ_CASC = 0; /双序列； AdcRegs.ADCTRL3.bit.SMODE_SEL = 0; /顺序采样AdcR

12、egs.ADCTRL1.bit.CONT_RUN = 0; /启停方式AdcRegs.ADCTRL1.bit.CPS = 1; /核时钟预定标器；/:ADC_CLK=ADCLKPS/2=3.125MAdcRegs.ADCTRL1.bit.ACQ_PS = 0xf; /采样窗口AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x2;/:ADCLKPS=HSPCLK/4=6.25M ；AdcRegs.ADCMAXCONV.all = 0x0000; /转换通道数:1 AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0xf; /通道62ADC Control Reg

13、ister 1 - Lower ByteADCTRL1 0x007100Continuous RunSequencer Mode0 = stops after reaching0 = dual modeend of sequence1 = cascaded mode 1 = continuous (starts all overagain from “initial state”)76543210Conversion PrescaleSequencer Override0 = CLK / 1(continuous run mode)1 = CLK / 20 = sequencer pointe

14、r resets to “initial state”at end of MAX_CONVn1 = sequencer pointer resets to “initial state” after “end state”63CPSCONT_RUNSEQ1_OVRDSEQ_CASCF2812 ADC Clocking ExamplePLLCRHISPCPCLKIN (30 MHz)SYSCLKOUT(150 MHz)HSPCLK(150 MHz)To CPU1010bPCLKCR.ADCENCLK = 1000bADCTRL3ADCTRL1ADCCLK(25 MHz)FCLK(25 MHz)T

15、o ADCpipelineADCTRL10011bFCLK = HSPCLK/(2*ADCCLKPS)0bADCCLK = FCLK/(CPS+1)sampling window0111bsampling window = (ACQ_PS + 1)*(1/ADCCLK)Important: ADCCLK can be aum of 25 MHz!6ACQ_PSbitsCPS bitADCCLKPSbitsHSPCLKbitsDIVbitsADC Control Register 1 - Upper ByteADCTRL1 0x007100ADC Module ResetAcquisition

16、Time Prescale (S/H)0 = no effectValue = (binary+1)1 = reset (set back to 0* Time dependent on the “Conversion by ADC logic)Clock Prescale” bit (Bit 7 “CPS”)118Emulation Suspend Mode00 = Mode 0 free run (do not stop)01 = Mode 1 stop after current sequence 10 = Mode 2 stop after current conversion 11

17、= Mode 3 stop immediately65RESETSUSMOD1 SUSMOD0 ACQ_PS3ACQ_PS2ACQ_PS1ACQ_PS0um Conversion Channels RegisterADCMAXCONV 0x007102¨ Bit fields define theum number of auto conversions (binary+1)Cascaded ModeMAX_MAX_MAX_MAX_MAX_MAX_MAX_ CONV 2_2CONV 2_1CONV 2_0CONV 1_3CONV 1_2CONV 1_1CONV 1_0SEQ2Dual

18、 ModeSEQ1¨ Auto conversion session always starts with the “initial state” and continues sequentially until the “end state”, if allowed66SEQ1SEQ2CascadedInitial stateEnd stateCONV00CONV08CONV00CONV07CONV15CONV15ADC Input Channel Select Sequencing Control RegisterBits 15-12Bits 11-8Bits 7-4Bits 3

19、-00x007103ADCCHSELSEQ10x007104ADCCHSELSEQ20x007105ADCCHSELSEQ30x007106ADCCHSELSEQ467CONV03CONV02CONV01CONV00CONV07CONV06CONV05CONV04CONV11CONV10CONV09CONV08CONV15CONV14CONV13CONV12ADC_实验（5）；while (1)int e=0;AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1; /S/W启动while (AdcRegs.ADCST.bit.SEQ1_BSY = 1) /忙否AD1 = AdcRe

20、gs.ADCRESULT0 >> 4;AD2=(AD1*3*1000)/4095;/实际AD值*1000 ； e+;if(e>0)/下页说明LEDdisplay(AD2/1000)+20,(AD2%1000)/100, (AD2%100)/10, 19, AD1/1000, (AD1%1000)/100,(AD1%100)/10,AD1%10); e=0;68ADC Control Register 2 - Upper ByteADCTRL2 0x007101EVB SOC(cascaded mode only)0 = no actionEVA SOCSEQ1 Mask Bi

21、t0 = cannot be started by EVA trigger1 = can be started by EVA trigger1 = start by EVBStart Conversion (SEQ1)signal0 = clear pending SOC trigger 1 = software trigger-start SEQ1118EVA_SOC_ SEQ1INT_ENA_ SEQ1EVB_SOC RST_SEQ1INT_MOD_SEQ1SOC_SEQ1_SEQInterrupt Enable (SEQ1)0 = interrupt disableReset SEQ10

22、 = no action1 = immediate reset SEQ1 to “initial state”Interrupt Mode (SEQ1)1 = interrupt enable0 = interrupt every EOS1 = interrupt every other EOS69模数转换状态和标志寄存器（ADCST）158 eserved52；1，0保留位读出值为0，写入操作无效。620158R-076543210EOS BUF2EOS BUF1INT SEQ2 CLRINT SEQ1 CLRSEQ2 BSYSEQ1 BSYINT SEQ2INT SEQ1R-0R-0R/W

23、-0R/W-0R-0R-0R-0R-0位5INT SEQ2 CLR SEQ2中断清零位。读出值为0。写入1清零。0 写入0无效1 写入1，对SEQ2中断标志位（INT_SEQ2）清零位4INT SEQ1 CLR SEQ1中断清零位。读出值为0。写入1清零。0 写入0无效1 写入1，对SEQ1中断标志位（INT_SEQ1）清零位 3SEQ2 BSYSEQ2忙状态位。写入操作无效。0 SEQ2空闲，等待触发1 SEQ2忙位 2SEQ1 BSYSEQ1忙状态位。写入操作无效。0 SEQ1空闲，等待触发1 SEQ1忙62位1INT SEQ2SEQ2中断标志位，写入操作无效。在中断模式0（ADCTRL2

24、20）下，该位在每一个SEQ2排序结1；在中断模式1（ADCTRL221）下，如果EOS_BUF21，该位在SEQ2排序结束后置1。01无SEQ2中断发生了SEQ2中断622位0作无效。INT SEQ1SEQ1中断标志位，写入操在中断模式0（ADCTRL2100）下，该位在每一个SEQ1排序结1；在中断模式1（ADCTRL2101）下，如果EOS_BUF11，该位在SEQ1排序结束后置1。01无SEQ1中断发生了SEQ1中断623How do we Read the Result?Integer formatxRESULTxbit shift right150ACCxData MemExamp

25、le: read RESULT0 register62#include "DSP281x_Device.h"void main(void)Uint16 value;/ unsignedvalue = AdcRegs.ADCRESULT0 >> 4;0000x00000000000000000000ADC Conversion Result Buffer RegisterADCRESULT0 0x007108 through ADCRESULT15 0x007117(Total of 16 Registersith analog input 0V to 3V, we have:analog voltsconverted valueRESULTx3.01.50.000730FFFh 7FFh1h0h1111|1111|1111|00000111|1111|1111|000