参考实验指导课件

1、实验5-2. 8位数码扫描显示电路设计程序设计与硬件实验LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SCAN_LED IS技PORT ( CLK SG BTEND; ARCHITECTURE oneSIGNAL CNT8: IN STD_LOGIC;: OUT STD_LOGIC_VECTOR(6: OUT STD_LOGIC_VECTOR(7DOWNTO DOWNTO0); -制信号输出0);-位信号输出OF SCAN_LED IS: STD_LOGIC_VECTOR(2

2、DOWNTO 0);: INTEGER RANGE 0 TO 15;SIGNAL BEGINAP1:PROCESS( BEGINCASECNT8 )CNT8 ISWHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN"000""001""010""011""100""101""110""111"=>=>=>=>=>=>=>=>BT BT BT BT BT

3、BT BT BT<=<=<=<=<=<=<=<="00000001""00000010""00000100""00001000""00010000""00100000""01000000""10000000"A A A A A A A A<=<=<=<=<=<=<=<=13579;11 ;13 ;15 ;OTHERS =>NULLEND

4、 CASE ;END PROCESS P1; P2: PROCESS(CLK)BEGINIF CLK'EVENT AND CLK = '1' END IF;END PROCESS P2 ;THEN CNT8<=CNT8+ 1;-译码电路P3: PROCESS( A ) BEGINCASE WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHENA 02468101214IS=>=>=>=>=>=>=>=>SG SG SG SG SG SG SG SG<=<=<=<

5、;=<=<=<=<="0111111""1011011""1100110""1111101""1111111""1110111""0111001""1111001"WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHE>=>=>=>=>=>=>=>SG SG SG SG SG SG SG SG<=<=<

6、;=<=<=<=<=<="0000110""1001111""1101101""0000111""1101111""1111100""1011110""1110001"OTHERS => NULL ;END CASE ;END PROCESS P3;END;科技KX模式5的电路结构K1K8为数码管的位控信号，对应FPGA的PIO41、40、39、38、37、36、35、34ag为数码管的信号，对应FPGA的PIO49、48、47、46、45、44、43、42引脚锁定科技KXBT7.0是位控信号，接PIO34、PIO41、SG7.0是信号，接PIO42、PIO49、选择JTAG模式用此纽选择编程 接口ByteblasterMV文件