基于EDA的交通灯控制器课程设计

1、本科课程设计报告课程名称： EDA计数与FPGA应用设计 设计题目： 交通灯控制器 实验地点： 跨越机房 专业班级： 电信0901 学号： 2009001249 学生姓名： 赵岩 指导教师： 张文爱 年 月 日 设计一：三位十进制计数显示器一、 设计目的：1、 掌握时序电路中多进程的VHDL的描述方法。2、 掌握层次化设计方法。3、熟悉EDA的仿真分析和硬件测试技术。二、设计原理三位十进制计数显示器分三部分完成，先设计十进制计数电路，再设计显示译码电路，最后设计一个顶层文件将两者连接起来。三源程序1、 三位十进制计数器的三位分三个进程描述，含有同步清0信号RESET和计数使能控制信号CINLI

2、BRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COU3 IS PORT(CLK,RESET,CIN:IN STD_LOGIC; CO:OUT STD_LOGIC; A,B,C:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END COU3 ;ARCHITECTURE ART OF COU3 IS SIGNAL AP,BP,CP:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN KK1:PROCESS(CLK) BEGIN IF (CLK

3、9;EVENT AND CLK='1') THEN IF (RESET='0') THEN AP<="0000" ELSIF (CIN='1') THEN IF (AP="1001") THEN AP<="0000" ; ELSE AP<=AP+'1' END IF; END IF; END IF; END PROCESS KK1;KK2:PROCESS(CLK) BEGIN IF (CLK'EVENT AND CLK='1')

4、THEN IF (RESET='0') THEN BP<="0000" ELSIF (CIN='1') AND (AP="1001") THEN IF BP="1001" THEN BP<="0000" ELSE BP<=BP+'1' END IF; END IF; END IF; END PROCESS KK2;KK3: PROCESS(CLK) BEGIN IF (CLK'EVENT AND CLK='1') THEN I

5、F (RESET='0') THEN CP<="0000" ELSIF (CIN='1') AND (AP="1001") AND (BP="1001") THEN IF CP="1001" THEN CP<="0000" ELSE CP<=CP+'1' END IF; END IF; END IF; END PROCESS KK3;PROCESS(CLK) IS BEGIN IF CLK'EVENT AND CLK=&#

6、39;1' THEN IF AP="1001" AND BP="1001" AND CP="1001" THEN CO<='1' ELSE CO<='0' END IF; END IF; END PROCESS; A<=AP; B<=BP; C<=CP;END ART;2、七段显示译码电路VHDL设计文件LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY YIMA7 IS PORT(A:IN STD_LOGIC_VECT

7、OR(3 DOWNTO 0); YIMA:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); END YIMA7; ARCHITECTURE ART OF YIMA7 IS BEGIN PROCESS(A) IS BEGIN CASE A IS WHEN "0000"=>YIMA<="1000000" WHEN "0001"=>YIMA<="1111001" WHEN "0010"=>YIMA<="0100100" WHEN

8、 "0011"=>YIMA<="0110000" WHEN "0100"=>YIMA<="0011001" WHEN "0101"=>YIMA<="0010010" WHEN "0110"=>YIMA<="0000010" WHEN "0111"=>YIMA<="1111000" WHEN "1000"=>YIM

9、A<="0000000" WHEN "1001"=>YIMA<="0010000" WHEN OTHERS=>YIMA<="1111111" END CASE; END PROCESS; END ART;3、三位显示译码顶层文件LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JISHUXIANSHI IS PORT(CLK,RESET,EN:IN STD_LOGIC; SEG1,SEG2,SEG3:OUT STD_LOGIC_VECTOR

10、(6 DOWNTO 0);END JISHUXIANSHI; ARCHITECTURE ART OF JISHUXIANSHI IS COMPONENT YIMA7 PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); YIMA:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); END COMPONENT; COMPONENT COU3 PORT(CLK,RESET,CIN:IN STD_LOGIC; CO:OUT STD_LOGIC; A,B,C:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END COMPONENT; SI

11、GNAL IN_A,IN_B,IN_C:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN U0:COU3 PORT MAP(CLK,RESET,EN,IN_A,IN_B,IN_C); U1:YIMA7 PORT MAP(IN_A,SEG1); U2:YIMA7 PORT MAP(IN_B,SEG2); U3:YIMA7 PORT MAP(IN_C,SEG3);END ART;四、仿真出图五、下载到电路板得到设计结果显示三位十进制计数设计二：交通灯控制器一、设计要求设计一个由一条支干道和一条主干道的汇合点形成的十字交叉路口的交通灯控制器，主要要求如下：（1）.主、支干道各设

12、有一个绿、黄、红指示灯，两个显示数码管。（2）主干道处于常允许状态，两支干道有车来才允许通行。（3）当主、支干道有车时，两者交替通行，主干道每次放行45s，支干道每次放行25s，在每次由亮绿灯变成亮红灯转换过程中，要亮5s黄灯作为过渡，并进行减计时显示。二、 设计方案1、分模块设计1）、红、绿、黄灯控制模块，模块名JTDKZ；2）、倒计时传输、控制模块XSKZ；3）、倒计时45sCNT45s；4）、倒计时25sCNT25s；5）、倒计时5sCNT05s。6）、输入、输出。2、模块设计思路1)、JTDKZ根据交通灯显示有4种状态，可以采用CASE语句设置选择4种状态。设置3个输入：CLK(时钟脉

13、冲)、SB(支干道传感器)、SM(主干道传感器)。2)、XSKZ根据需要交通灯显示的不同数倒计时据设置4个输入使能信号：EN45(45s倒计时使能信号)、EN25(25s倒计时使能信号)、EN05(5s倒计时使能信号)；再设置5个倒计时计数数据输入信号将此时倒计时数据输出：AIN45M、AIN45B、AIN25M、AIN25B、AIN05；2个输出信号使数码管显示正在倒计时的时间。3)、CNT45S根据倒计时计数的要求设置3个输入信号：CLK(计数脉冲)、EN45(计数使能)、SB(支干道传感器信号)；2个输出DOUT45M、DOUT45B，分别用于主、支干道显示。 4)、CNT25s根据倒计

14、时计数的要求设置4个输入信号：CLK(计数脉冲)、EN45(计数使能)、SM(主干道传感器信号)、SB(支干道传感器信号)；2个输出DOUT25M、DOUT25B，分别用于主、支干道显示。 5)、CNT05s根据倒计时计数的要求设置3个输入信号：CLK(计数脉冲)、EN05B(计数使能)、EN05M(计数使能)；1个输出DOUT05，用于主、支干道显示。 6)、输入输出模块，3个输入分别为：CLK、SB、SM，2个输出分别为DOUT17.0、DOUT27.0。三、设计源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JTDKZ IS POR

15、T(CLK,SM,SB:IN STD_LOGIC; MR,MY0,MG0,BR,BY0,BG0:OUT STD_LOGIC);END ENTITY JTDKZ;ARCHITECTURE ART OF JTDKZ IS TYPE STATE_TYPE IS(A,B,C,D); SIGNAL STATE:STATE_TYPE; BEGIN CNT:PROCESS(CLK)IS VARIABLE S:INTEGER RANGE 0 TO 45; VARIABLE CLR,EN:BIT; BEGIN IF(CLK'EVENT AND CLK='1')THEN IF CLR=&#

16、39;0'THEN S:=0; ELSIF EN='0'THEN S:=S; ELSE S:=S+1; END IF; CASE STATE IS WHEN A=>MR<='0'MY0<='0'MG0<='1'BR<='1'BY0<='0'BG0<='0' IF(SB AND SM)='1' THEN IF S=45 THEN STATE<=B;CLR:='0'EN:='0' EL

17、SE STATE<=A;CLR:='1'EN:='1' END IF; ELSIF(SB AND(NOT SM)='1'THEN STATE<=B;CLR:='0'EN:='0' ELSE STATE<=A;CLR:='1'EN:='1' END IF; WHEN B=>MR<='0'MY0<='1'MG0<='0'BR<='1'BY0<='0'BG0

18、<='0' IF S=5 THEN STATE<=C;CLR:='0'EN:='0' ELSE STATE<=B;CLR:='1'EN:='1' END IF; WHEN C=>MR<='1'MY0<='0'MG0<='0'BR<='0'BY0<='0'BG0<='1' IF(SM AND SB)='1'THEN IF S=25 THEN STA

19、TE<=D;CLR:='0'EN:='0' ELSE STATE<=C;CLR:='1'EN:='1' END IF; ELSIF SB='0' THEN STATE<=D;CLR:='0'EN:='0' ELSE STATE<=C;CLR:='1'EN:='1' END IF; WHEN D=>MR<='1'MY0<='0'MG0<='0'BR<=&

20、#39;0'BY0<='1'BG0<='0' IF S=5 THEN STATE<=A;CLR:='0'EN:='0' ELSE STATE<=D;CLR:='1'EN:='1' END IF; END CASE; END IF;END PROCESS CNT;END ARCHITECTURE ART;设计仿真的截图：XSKZ模块的实现简单设计思路：根据EN45、EN25、EN05M、EN05B的信号以及3个倒计时计数器的计数状态决定输出3个倒计时计数器中某个的状态输

21、出。原理图模块：设计源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CSKZ IS PORT(INA:IN STD_LOGIC; OUTA:OUT STD_LOGIC);END ENTITY CSKZ;ARCHITECTURE ART OF CSKZ IS BEGIN PROCESS(INA)IS BEGIN IF INA='1'THEN OUTA<='1' ELSE OUTA<='0' END IF; END PR

22、OCESS;END ARCHITECTURE ART;设计仿真的截图：CNT45S模块的实现简单思路：CLK上升沿到来时，若到计时使能信号和SB信号有效，CNT45S开始计数，并将输入状态通过DOUT45M、DOUT45B分别输出到主、支干道显示。 设计的原理图模块： 设计源程序：3LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT45S IS PORT(SB,CLK,EN45:IN STD_LOGIC; DOUT45M,DOUT45B:OUT STD_LOGIC_VECTOR(

23、7 DOWNTO 0);END CNT45S;ARCHITECTURE ART OF CNT45S IS SIGNAL CNT6B:STD_LOGIC_VECTOR(5 DOWNTO 0); BEGIN PROCESS(SB,CLK,EN45) IS BEGIN IF SB='0' THEN CNT6B<=CNT6B-CNT6B-1; ELSIF(CLK'EVENT AND CLK='1')THEN IF EN45='1'THEN CNT6B<=CNT6B+1; ELSIF EN45='0'THEN CNT6B

24、<=CNT6B-CNT6B-1; END IF;END IF;END PROCESS;PROCESS(CNT6B)ISBEGINCASE CNT6B ISWHEN"000000"=>DOUT45M<="01000101"DOUT45B<="01010000"WHEN"000001"=>DOUT45M<="01000100"DOUT45B<="01001001"WHEN"000010"=>DOUT45M<

25、="01000011"DOUT45B<="01001000"WHEN"000011"=>DOUT45M<="01000010"DOUT45B<="01000111"WHEN"000100"=>DOUT45M<="01000001"DOUT45B<="01000110"WHEN"000101"=>DOUT45M<="01000000"DOUT45

26、B<="01000101"WHEN"000110"=>DOUT45M<="00111001"DOUT45B<="01000100"WHEN"000111"=>DOUT45M<="00111000"DOUT45B<="01000011"WHEN"001000"=>DOUT45M<="00110111"DOUT45B<="01000010"W

27、HEN"001001"=>DOUT45M<="00110110"DOUT45B<="01000001"WHEN"001010"=>DOUT45M<="00110101"DOUT45B<="01000000"WHEN"001011"=>DOUT45M<="00110100"DOUT45B<="01101001"WHEN"001100"=>D

28、OUT45M<="00110011"DOUT45B<="00111000"WHEN"001101"=>DOUT45M<="00110010"DOUT45B<="00110111"WHEN"001110"=>DOUT45M<="00110001"DOUT45B<="00110110"WHEN"001111"=>DOUT45M<="00110000&q

29、uot;DOUT45B<="00110101"WHEN"010000"=>DOUT45M<="00101001"DOUT45B<="00110100"WHEN"010001"=>DOUT45M<="00101000"DOUT45B<="00110011"WHEN"010010"=>DOUT45M<="00100111"DOUT45B<="00110

30、010"WHEN"010011"=>DOUT45M<="00100110"DOUT45B<="00110001"WHEN"010100"=>DOUT45M<="00100101"DOUT45B<="00110000"WHEN"010101"=>DOUT45M<="00100100"DOUT45B<="00101001"WHEN"010110&q

31、uot;=>DOUT45M<="00100011"DOUT45B<="00101000"WHEN"010111"=>DOUT45M<="00100010"DOUT45B<="00100111"WHEN"011000"=>DOUT45M<="00100001"DOUT45B<="00100110"WHEN"011001"=>DOUT45M<="

32、00100000"DOUT45B<="00100101"WHEN"011010"=>DOUT45M<="00011001"DOUT45B<="00100100"WHEN"011011"=>DOUT45M<="00011000"DOUT45B<="00100011"WHEN"011100"=>DOUT45M<="00010111"DOUT45B<=&

33、quot;00100010"WHEN"011101"=>DOUT45M<="00010110"DOUT45B<="00100001"WHEN"011110"=>DOUT45M<="00010101"DOUT45B<="00100000"WHEN"011111"=>DOUT45M<="00010100"DOUT45B<="00011001"WHEN&quo

34、t;100000"=>DOUT45M<="00010011"DOUT45B<="00011000"WHEN"100001"=>DOUT45M<="00010010"DOUT45B<="00010111"WHEN"100010"=>DOUT45M<="00010001"DOUT45B<="00010110"WHEN"100011"=>DOUT45M&

35、lt;="00010000"DOUT45B<="00010101"WHEN"100100"=>DOUT45M<="00001001"DOUT45B<="00010100"WHEN"100101"=>DOUT45M<="00001000"DOUT45B<="00010011"WHEN"100110"=>DOUT45M<="00000111"DOU

36、T45B<="00010010"WHEN"100111"=>DOUT45M<="00000110"DOUT45B<="00010001"WHEN"101000"=>DOUT45M<="00000101"DOUT45B<="00010000"WHEN"101001"=>DOUT45M<="00000100"DOUT45B<="00001001&quo

37、t;WHEN"101010"=>DOUT45M<="00000011"DOUT45B<="00001000"WHEN"101011"=>DOUT45M<="00000010"DOUT45B<="00000111"WHEN"101100"=>DOUT45M<="00000001"DOUT45B<="00000110"WHEN OTHERS=>DOUT45M&l

38、t;="00000000"DOUT45B<="00000000"END CASE;END PROCESS;END;设计仿真的截图：CNT25S模块的实现简单思路：CLK上升沿到来时，若到计时使能信号、SM信号和SB信号有效，CNT25S开始计数，并将输入状态通过DOUT25M、DOUT25B分别输出到主、支干道显示。设计的原理图模块：设计源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSI GNED.ALL;ENTITY CNT25S IS PORT(SB,SM,C

39、LK,EN25:IN STD_LOGIC; DOUT25M,DOUT25B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY CNT25S;ARCHITECTURE ART OF CNT25S IS SIGNAL CNT5B:STD_LOGIC_VECTOR(4 DOWNTO 0); BEGINPROCESS(SB,SM,CLK,EN25)ISBEGIN IF SB='0'THEN CNT5B<=CNT5B-CNT5B-1; ELSIF SM='0'THEN CNT5B<=CNT5B-CNT5B-1; ELSIF

40、(CLK'EVENT AND CLK='1')THEN IF EN25='1'THEN CNT5B<=CNT5B+1; ELSIF EN25='0'THEN CNT5B<=CNT5B-CNT5B-1; END IF; END IF; END PROCESS; PROCESS(CNT5B)IS BEGIN CASE CNT5B IS WHEN"00000"=>DOUNT25B<="00100101"DOUT25M<="00110000" WHEN&qu

41、ot;00001"=>DOUNT25B<="00100100"DOUT25M<="00101001" WHEN"00010"=>DOUNT25B<="00100011"DOUT25M<="00101000" WHEN"00011"=>DOUNT25B<="00100010"DOUT25M<="00100111" WHEN"00100"=>DOUNT

42、25B<="00100001"DOUT25M<="00100110" WHEN"00101"=>DOUNT25B<="00100000"DOUT25M<="00100101" WHEN"00110"=>DOUNT25B<="00011001"DOUT25M<="00100100" WHEN"00111"=>DOUNT25B<="00011000&q

43、uot;DOUT25M<="00100011" WHEN"01000"=>DOUNT25B<="00010111"DOUT25M<="00100010" WHEN"01001"=>DOUNT25B<="00010110"DOUT25M<="00100001" WHEN"01010"=>DOUNT25B<="00010101"DOUT25M<="00

44、100000" WHEN"01011"=>DOUNT25B<="00010100"DOUT25M<="00011001" WHEN"01100"=>DOUNT25B<="00010011"DOUT25M<="00011000" WHEN"01101"=>DOUNT25B<="00010010"DOUT25M<="00010111" WHEN"0

45、1110"=>DOUNT25B<="00010001"DOUT25M<="00010110" WHEN"01111"=>DOUNT25B<="00010000"DOUT25M<="00010101" WHEN"10000"=>DOUNT25B<="00001001"DOUT25M<="00010100" WHEN"10001"=>DOUNT25B&

46、lt;="00001000"DOUT25M<="00010011" WHEN"10010"=>DOUNT25B<="00000111"DOUT25M<="00010010" WHEN"10011"=>DOUNT25B<="00000110"DOUT25M<="00010001" WHEN"10100"=>DOUNT25B<="00000101"

47、DOUT25M<="00010000" WHEN"10101"=>DOUNT25B<="00000100"DOUT25M<="00001001" WHEN"10110"=>DOUNT25B<="00000011"DOUT25M<="00001000" WHEN"10111"=>DOUNT25B<="00000010"DOUT25M<="000001

48、11" WHEN"11000"=>DOUNT25B<="00000001"DOUT25M<="00000110" WHEN OTHERS=>DOUNT25B<="00000000"DOUT25M<="00000000"END CASE;END PROCESS;END;设计仿真的截图：CNT05S模块的实现简单思路：CLK上升沿到来时，若到计时使能信号有效，CNT25S开始计数，并将输入状态通过DOUT05输出到主、支干道显示。设计的原理图模块：设计源

49、程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT05S ISPORT(CLK,EN05M,EN05B:IN STD_LOGIC; DOUT5:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END CNT05S;ARCHITECTURE ART OF CNT05S IS SIGNAL CNT3B:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN PROCESS(CLK,EN05M,EN05B)IS BEGIN IF(CLK'E

50、VENT AND CLK='1')THEN IF EN05M='1'THEN CNT3B<=CNT3B+1; ELSIF EN05B='1'THEN CNT3B<=CNT3B+1; ELSIF EN05B='0'THEN CNT3B<=CNT3B-CNT3B-1; END IF; END IF; END PROCESS; PROCESS(CNT3B) BEGIN CASE CNT3B IS WHEN"000"=>DOUT5<="00000101" WHEN&qu

51、ot;001"=>DOUT5<="00000100" WHEN"010"=>DOUT5<="00000011" WHEN"011"=>DOUT5<="00000010" WHEN"100"=>DOUT5<="00000001" WHEN OTHERS=>DOUT5<="00000000" END CASE; END PROCESS;END;设计仿真的截图：显示译码器L

52、IBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY YIMA7 IS PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); YIMA:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); END YIMA7; ARCHITECTURE ART OF YIMA7 IS BEGIN PROCESS(A) IS BEGIN CASE A IS WHEN "0000"=>YIMA<="1000000" WHEN "0001"=>YIMA<

53、;="1111001" WHEN "0010"=>YIMA<="0100100" WHEN "0011"=>YIMA<="0110000" WHEN "0100"=>YIMA<="0011001" WHEN "0101"=>YIMA<="0010010" WHEN "0110"=>YIMA<="0000010" WHE

54、N "0111"=>YIMA<="1111000" WHEN "1000"=>YIMA<="0000000" WHEN "1001"=>YIMA<="0010000" WHEN "1010"=>YIMA<="0001000" WHEN "1011"=>YIMA<="0000011" WHEN "1100"=>YI

55、MA<="1000110" WHEN "1101"=>YIMA<="0100001" WHEN "1110"=>YIMA<="0000110" WHEN "1111"=>YIMA<="0001110" WHEN OTHERS=>NULL; END CASE; END PROCESS; END ART;整体组装和测试自动转换出来的源程序：LIBRARY ieee;USE ieee.std_logic_1164.

56、all; LIBRARY work;ENTITY Block1 IS port( CLK : IN STD_LOGIC;SM : IN STD_LOGIC;SB : IN STD_LOGIC;MR : OUT STD_LOGIC;MY : OUT STD_LOGIC;MG : OUT STD_LOGIC;BR : OUT STD_LOGIC;BY : OUT STD_LOGIC;BG : OUT STD_LOGIC;DOUT1 : OUT STD_LOGIC_VECTOR(7 downto 0);DOUT2 : OUT STD_LOGIC_VECTOR(7 downto 0);END Bloc

57、k1;ARCHITECTURE bdf_type OF Block1 IS component cnt05sPORT(CLK : IN STD_LOGIC; EN05M : IN STD_LOGIC; EN05B : IN STD_LOGIC; DOUT5 : OUT STD_LOGIC_VECTOR(7 downto 0);end component;component cnt25sPORT(SB : IN STD_LOGIC; SM : IN STD_LOGIC; CLK : IN STD_LOGIC; EN25 : IN STD_LOGIC; DOUT25B : OUT STD_LOGI

58、C_VECTOR(7 downto 0); DOUT25M : OUT STD_LOGIC_VECTOR(7 downto 0);end component;component cnt45sPORT(SB : IN STD_LOGIC; CLK : IN STD_LOGIC; EN45 : IN STD_LOGIC; DOUT45B : OUT STD_LOGIC_VECTOR(7 downto 0); DOUT45M : OUT STD_LOGIC_VECTOR(7 downto 0);end component;component jtdkzPORT(CLK : IN STD_LOGIC;

59、 SM : IN STD_LOGIC; SB : IN STD_LOGIC; MR : OUT STD_LOGIC; MY0 : OUT STD_LOGIC; MG0 : OUT STD_LOGIC; BR : OUT STD_LOGIC; BY0 : OUT STD_LOGIC; BG0 : OUT STD_LOGIC);end component;component xskzPORT(EN45 : IN STD_LOGIC; EN25 : IN STD_LOGIC; EN05M : IN STD_LOGIC; EN05B : IN STD_LOGIC; AIN05 : IN STD_LOG

60、IC_VECTOR(7 downto 0); AIN25B : IN STD_LOGIC_VECTOR(7 downto 0); AIN25M : IN STD_LOGIC_VECTOR(7 downto 0); AIN45B : IN STD_LOGIC_VECTOR(7 downto 0); AIN45M : IN STD_LOGIC_VECTOR(7 downto 0); DOUTB : OUT STD_LOGIC_VECTOR(7 downto 0); DOUTM : OUT STD_LOGIC_VECTOR(7 downto 0);end component;signalSYNTHESIZED_WIRE_13 : STD_LOGIC;signalSYNTHESIZED_WIRE_14 : STD_LOGIC;signalSYNTHE