基于FPGA的广告显示屏的设计

1、电子设计自动化基于FPGA的广告显示屏的设计 学院：通信与信息工程学院 专业： 通信与信息系统 姓名： 樊 忠 S100101025 一 需求分析1.功能描述：随着现在经济的飞速发展，城市的建设与美观也越来越正规化。广告的设计与要求也越来越严格，环顾我们周围，广告商满大街的拉横幅。虽然起到了很大的宣传作用，但让城市的美观降低了层次，同时也增加了很大的安全隐患。用电子广告显示屏来做宣传，不仅美观大方，可以根据实际需要，对广告内容及时修改。不会像其它形式的广告宣传产生巨大的资源消耗，环境污染符合当今低碳生活要求。 2.其他要求：本设计可以直接运行教学实验箱的模式七。二 总体设计1.设计思路参考LC

2、D12864资料，由verilog语言对电子广告显示屏的中文显示，时间显示，时间调节等功能进行描述，实现电子广告显示屏的功能。同时独立按键可以对显示屏进行实时时间调节。2.器件选择 Cyclone III LCD12864 独立按键3.开发环境 Quartus II EDA教学实验箱三硬件设计1.系统电路图该系统电路主要功能：系统开始工作后，12864自动显示预设中文字符，在液晶的最后一行显示时间，可以通过独立按键对月，日，时，分，秒进行调整。2各模块电路图2.1时钟分频模块 LCD时钟分频信号模块 时间显示计数分频信号模块通过对系统时钟进行分频，得到clk_lcd和clk1，分别驱动1286

3、4和计时时钟信号。2.2计时显示模块 计时显示模块 计时显示模块是系统的核心模块。系统开始工作后，LCD显示预设中文字符，在液晶的最后一行显示时间，可以通过按键对月，日，时，分，秒进行调整。四软件设计1.信号流程图2.模块信号流程图2.1计数信号流程图通过对系统时钟的分频，来达到驱动液晶和芯片工作的目的。2.2计时调时信号流程图通过实时查询来判断月，日，时，分，秒。按键可以随时调整显示的时间。五测试结果在EDA实验箱上运行，结果显示如下，达到设计预期目的。六问题分析 对功能寄存器的正确操作是操作LCD12864的重要工作组成部分。最初上电实验时，液晶无任何显示的主要原因就是没有正确操作寄存器。

4、七总结经过一学期的紧张学习，我们基本掌握了电子设计的设计流程，熟练使用keil软件，protues软件，Quartus II软件，能通过实践来实现一些小题目，达到了预期的学习目标。借此机会向一直兢兢业业工作的张老师表示感谢，向一直共同进取，相互学习的同学表示感谢。在今后的日子里，我们会更加努力学习，积极进取，努力在硬件设计方面做出些成绩。参考文献1 夏宇闻. Verilog数字系统设计M.北京：北京航空航天大学出版社.2008.2 吴厚航. 深入浅出玩转FPGAM .北京：北京航空航天大学出版社.2010.3 4附程序代码：时钟分频程序模块module divclk_clk1(CLK_LCD,

5、rst,clk1);input CLK_LCD,rst;output clk1;reg clk1;reg 15:0 cnt2;always (posedge CLK_LCD or negedge rst) begin if (!rst)/rst按键按下 为低电平begincnt2 <= 16'b0;clk1 <= 0;end else if(cnt2 = 49)begincnt2 <= 0;clk1 <= clk1;end elsecnt2 <= cnt2 +1'b1;endendmodulemodule divclk_lcd(clk0,rst,c

6、lk_lcd);input clk0,rst;output clk_lcd;reg CLK_LCD;/LCD时钟信号reg 23:0cnt1;always (posedge clk0 or negedge rst) begin if (!rst) begincnt1 <= 24'b0;CLK_LCD <= 0;end else if(cnt1 = 199999)begincnt1 <= 0;CLK_LCD <= CLK_LCD;end else cnt1 <= cnt1 +1'b1;endendmodule计时调时模块module lcd_time

7、_key(clk0,clk1,rst,key4,key3,key2,key1,key0,month,day,hour,min,sec);input clk0,clk1,rst,key4,key3,key2,key1,key0;output month7:4,month3:0,day7:4,day3:0,hour7:4,hour3:0, min7:4,min3:0,sec7:4,sec3:0; reg 7:0 hour,min,sec; reg 7:0 month,day;wire seccar,mincar; always (posedge temp_sec) begin if(sec = 8

8、'h59) beginsec <= 0; end else if(sec3:0 = 9) beginsec3:0 <= 0;sec7:4 <= sec7:4 + 1; end else sec3:0 <= sec3:0 + 1; endassign seccar=(sec = 8'h59)?1:0; always (negedge temp_min) begin if(min = 8'h59) beginmin <= 0; end else if(min3:0 = 9) beginmin3:0 <= 0;min7:4 <= mi

9、n7:4 + 1; end else min3:0 <= min3:0 + 1; endassign mincar=(min = 8'h59)?1:0; always (negedge temp_hour) begin if(hour = 8'h23) beginhour <= 0; end else if(hour3:0 = 9) beginhour3:0 <= 0;hour7:4 <= hour7:4 + 1; end else hour3:0 <= hour3:0 + 1;endalways (negedge temp_month) begi

10、n if(month = 8'h12) beginmonth <= 0; end else if(month3:0 = 9) beginmonth3:0 <= 0;month7:4 <= month7:4 + 1; end else month3:0 <= month3:0 + 1;endalways (negedge temp_day) begin if(day = 8'h31) beginday <= 0; end else if(day3:0 = 9) beginday3:0 <= 0;day7:4 <= day7:4 + 1;

11、end else day3:0 <= day3:0 + 1;endreg4:0 key_rst; always (posedge clk0 or negedge rst) if(!rst) key_rst <= 5'b11111; elsekey_rst<= key4,key3,key2,key1,key0;reg4:0 key_rst_r; always ( posedge clk0 or negedge rst )if (!rst) key_rst_r <= 5'b11111;else key_rst_r <= key_rst;wire4:0

12、key_an = key_rst_r & ( key_rst);reg19:0 cnt; always (posedge clk0 or negedge rst) if(!rst) cnt <= 20'd0; else if(key_an) cnt <=20'd0; else cnt <= cnt + 1'b1;reg4:0 low_sw;always (posedge clk0 or negedge rst)if (!rst) low_sw <= 5'b11111;else if (cnt = 20'hfffff) lo

13、w_sw <= key4,key3,key2,key1,key0;reg 4:0 low_sw_r; always (posedge clk0 or negedge rst) if(!rst) low_sw_r <= 5'b11111; else low_sw_r <= low_sw;wire4:0 sw_ctrl = low_sw_r4:0&(low_sw4:0);wire temp_sec,temp_min,temp_hour,temp_month,tri_day;assign temp_sec = sw_ctrl0 | clk1;assign temp_

14、min = sw_ctrl1 | seccar;assign temp_hour = sw_ctrl2 | mincar;assign temp_month = sw_ctrl3;assign temp_day = sw_ctrl4;endmodule液晶初始化模块：reg8:0 state;parameterIDLE = 9'b00000000,CLEAR= 9'b00000001, SETFUNCTION= 9'b00000010, SWITCHMODE= 9'b00000100, SETMODE = 9'b00001000,SHIFT = 9

15、9;b00010000,SETDDRAM = 9'b00100000, WRITERAM = 9'b01000000, STOP= 9'b10000000; reg flag;reg 6:0char_cnt;reg 7:0data_disp;assign RW = 1'b0;ssign EN = (flag = 1)?CLK_LCD:1'b0;always (posedge CLK_LCD or negedge rst)beginif(!rst)RS <= 1'b0;else if(state = WRITERAM)RS <= 1&#

16、39;b1;elseRS <= 1'b0;endalways (posedge CLK_LCD or negedge rst)/State Machine beginif(!rst)beginstate <= IDLE;DATA <= 8'bzzzzzzzz;char_cnt <= 5'b0;flag <= 1'b1;endelsebegincase(state)IDLE:begin flag <= 1'b1;state <= CLEAR;DATA<=8'bzzzzzzzz;endCLEAR:beg

17、instate <= SETFUNCTION;DATA <= 8'b00000001;endSETFUNCTION:beginstate <= SWITCHMODE;DATA <= 8'b00110000;endSWITCHMODE:begintate <= SETMODE;DATA <= 8'b00001100;endSETMODE:beginstate <= SETDDRAM;DATA <= 8'b00000110;endbeginstate <= SETDDRAM;DATA <= 8'b0

18、001_0000;endSETDDRAM:beginstate <= WRITERAM;if(char_cnt = 0)beginDATA <= 8'b1000_0000;endelse if(char_cnt = 16)beginDATA <= 8'b1001_0000;endelse if(char_cnt = 32) begin DATA <= 8'b1000_1000; endelse if(char_cnt = 48) beginDATA<=8'b1001_1000; end endWRITERAM:beginif(cha

19、r_cnt <= 15) beginchar_cnt <= char_cnt + 1'b1; DATA <= data_disp;if(char_cnt = 15)state <= SETDDRAM;elsestate <= WRITERAM;endelse if(char_cnt >= 16 && char_cnt <= 31) beginchar_cnt <= char_cnt + 1'b1; DATA <= data_disp;if(char_cnt = 31)state <= SETDDRAM;

20、elsestate <= WRITERAM;end else if(char_cnt >= 32 && char_cnt <= 47) beginchar_cnt <= char_cnt + 1'b1; DATA <= data_disp;if(char_cnt = 47)state <= SETDDRAM;elsestate <= WRITERAM;endelse if(char_cnt >= 48 && char_cnt <= 64) beginDATA <= data_disp;if(ch

21、ar_cnt = 64)beginstate <= STOP;char_cnt <= 5'b0;flag <= 1'b0;endelsebeginstate <= WRITERAM; char_cnt <= char_cnt + 1'b1;endendendSTOP:begin flag <= 1'b1; state <= SETDDRAM; enddefault: state <= IDLE;endcaseendend显示模块：always (char_cnt)begincase (char_cnt)7'

22、d0: data_disp = 8'ha2; 7'd1: data_disp = 8'ha0; 7'd2: data_disp = 8'ha2; 7'd3: data_disp = 8'ha0; 7'd4: data_disp = 8'hbb; 7'd5: data_disp = 8'hb6; 7'd6: data_disp = 8'hd3; 7'd7: data_disp = 8'had; 7'd8: data_disp = 8'hb9; 7'd9:

23、 data_disp = 8'he2; 7'd10: data_disp = 8'hc1; 7'd11:data_disp=8'hd9; 7'd12: data_disp = 8'ha2;7'd13: data_disp = 8'ha0;7'd14: data_disp = 8'ha2; 7'd15: data_disp = 8'ha0; 7'd16: data_disp = 8'ha2; 7'd17: data_disp = 8'ha0; 7'd18

24、: data_disp = 8'hd6; 7'd19: data_disp = 8'hd8; 7'd20: data_disp = 8'hc7; 7'd21: data_disp = 8'hec; 7'd22: data_disp = 8'hd3; 7'd23: data_disp = 8'hca; 7'd24: data_disp = 8'hb5; 7'd25: data_disp = 8'he7; 7'd26: data_disp = 8'hb4; 7&#

25、39;d27: data_disp = 8'hf3; 7'd28: data_disp = 8'hd1; 7'd29: data_disp = 8'ha7; 7'd30: data_disp = 8'ha2;7'd31: data_disp = 8'ha0; 7'd32: data_disp = 8'ha2; 7'd33: data_disp = 8'ha0;7'd34: data_disp = 8'ha2; 7'd35: data_disp = 8'ha0;7'd36: data_disp = 8'ha2; 7'd37: data_disp = 8'ha0;7'd38: data_disp = 8'ha2; 7'd39: data_disp = 8'ha0;7'd40: data_disp = 8'ha2; 7'd41: data_disp = 8'ha0; 7'd42: data_disp = 8