EDA数码管动态扫描电路

1、数码管动态扫描电路设计试设计一个数码管动态显示的扫面控制电路。它能将8路位二进制数显示在实验箱上的8个数码管上。要求:当输入为0000-1001时显示为09,1010-1111时显示ABCDEF字母。先将该控制电路分为几个模块,然后用VHDL的结构化描述方式实现该电路。38译码器LIBRARY IEEE;ENTITY LIN_EDA ISPORT(ABC:IN STD_LOGIC_VECTOR(2 DOWNTO 0;BT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0 ;END;ARCHITECTURE ONE OF LIN_EDA ISBEGINPROCESS(ABCBEGI

2、NCASE ABC ISWHEN "000"=>BT<="00000001"WHEN "001"=>BT<="00000010"WHEN "010"=>BT<="00000100"WHEN "011"=>BT<="00001000"WHEN "100"=>BT<="00010000"WHEN "101"=>BT&

3、lt;="00100000"WHEN "110"=>BT<="01000000"WHEN "111"=>BT<="10000000"WHEN OTHERS=>NULL;END CASE;END PROCESS;END;3位二进制计数器LIBRARY IEEE;ENTITY OK_B ISPORT(CLK1:IN STD_LOGIC;Q:BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0;END;ARCHITECTURE BBC OF OK_B IS

4、SIGNAL Q1:STD_LOGIC_VECTOR(2 DOWNTO 0;BEGINPROCESS(CLKBEGINIF CLK1'EVENT AND CLK1='1' THENQ1<=Q1+1;END IF;END PROCESS;Q<=Q1;END;7段译码器LIBRARY IEEE;ENTITY DECL7S ISPORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0;LED7S:OUT STD_LOGIC_VECTOR(6 DOWNTO 0 ; END;ARCHITECTURE ONE OF DECL7S ISBEGINPROC

5、ESS(ABEGINCASE A ISWHEN "0000"=>DECL7S<="0111111"WHEN "0001"=>DECL7S<="0000110"WHEN "0010"=>DECL7S<="1011011"WHEN "0011"=>DECL7S<="1001111"WHEN "0100"=>DECL7S<="1100110"W

6、HEN "0101"=>DECL7S<="1101101"WHEN "0110"=>DECL7S<="1111101"WHEN "0111"=>DECL7S<="0000111"WHEN "1000"=>DECL7S<="1111111"WHEN "1001"=>DECL7S<="1101111"WHEN "1010"

7、=>DECL7S<="1110111"WHEN "1011"=>DECL7S<="1111100"WHEN "1100"=>DECL7S<="0111001"WHEN "1101"=>DECL7S<="1011110"WHEN "1110"=>DECL7S<="1111001"WHEN "1111"=>DECL7S<=&quo

8、t;1110001"WHEN OTHERS=>NULL;END CASE;END PROCESS;END;顶层文件LIBRARY IEEE;ENTITY sccbc_led ISPORT(B:IN STD_LOGIC_VECTOR(3 DOWNTO 0;LED7S1:OUT STD_LOGIC_VECTOR(6 DOWNTO 0;BT1:OUT STD_LOGIC_VECTOR(7 DOWNTO 0; END;ARCHITECTURE CNT_ABC OF sccbc_led IS COMPONENT LIN_EDAPORT(ABC:IN STD_LOGIC_VECTOR(2

9、DOWNTO 0;BT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0 ; END COMPONENT;COMPONENT OK_BPORT(CLK1:IN STD_LOGIC;Q:BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0; END COMPONENT;COMPONENT DECL7SPORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0;LED7S:OUT STD_LOGIC_VECTOR(6 DOWNTO 0 ; END COMPONENT;COMPONENT ABC_HPORT(B1:IN STD_LOGIC_VECTOR(

10、3 DOWNTO 0;Q:OUT INTEGER RANGE 0 TO 15 ;END COMPONENT;SIGNAL B:STD_LOGIC;SIGNAL A2:INTEGER;BEGINU1:ABC_H PORT MAP(B1=>B,A1=>A2;U2:DECL7S PORT MAP(A=>A2,LED7S=>LED7S1;U3:OK_B PORT MAP(CLK1=>CLK,Q=>B;U4:LIN_EDA PORT MAP(ABC=>B,BT=>BT1;END ARCHITECTURE CNT_ABC ;数据选择器LIBRARY IEEE

11、;ENTITY ABC_H ISPORT(B1:IN STD_LOGIC_VECTOR(3 DOWNTO 0;Q:OUT INTEGER RANGE 0 TO 15 ;END;ARCHITECTURE ABC_C OF ABC_H ISBEGINPROCESS(B1BEGINCASE B1 ISWHEN "0000"=>A1<=0; WHEN "0001"=>A1<=1; WHEN "0010"=>A1<=2; WHEN "0011"=>A1<=3; WHEN "0100"=>A1<=4; WHEN "0101"=>A1<=5; WHEN "0110"=>A1<=6; WHEN "0111"=>A1<=7; WHEN "1000"=>A1<=8; WHEN "1001"=>A1<=9; WHEN "1010"=>A1<=10; WHEN "1011"=>A1<=11; WHEN &q