quartus ii 常见的19个错误、28个警告

1、(一) Quartus警告解析 1.Found clock-sensitive change during active clock edge at time<time> on register "<name>"原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。而时钟敏感信号是不能在时钟边沿变化的。其后果为导致结果不正确。措施：编辑vector source file 2.Verilog HDL assignment warning at <location&

2、gt;: truncated with size <number> to match size of target (<number>原因:在HDL设计中对目标的位数进行了设定,如:reg4:0 a;而默认为32位,将位数裁定到合适的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数 3.All reachable assignments to data_out(10) assign '0', register removed by optimization原因:经过综合器优化后，输出端口已经不起作用了 4

3、.Following 9 pins have nothing, GND, or VCC driving datain port -changes to this connectivity may change fitting results原因:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋0，便会被接地，赋1接电源。如果你的设计中这些端口就是这样用的，那便可以不理会这些warning 5.Found pins functioning as undefined clocks and/or memory enables原因:是你作为时钟的PIN没有约束信息。可以

4、对相应的PIN做一下设定就行了。主要是指你的某些管脚在电路当中起到了时钟管脚的作用，比如flip-flop的clk管脚，而此管脚没有时钟约束，因此QuartusII把“clk”作为未定义的时钟。措施:如果clk不是时钟，可以加“not clock”的约束；如果是，可以在clock setting当中加入；在某些对时钟要求不很高的情况下，可以忽略此警告或在这里修改:Assignments>Timing analysis settings.>Individualclocks.>. 6.Timing characteristics of device EPM570T144

5、C5 are preliminary原因:因为MAXII 是比較新的元件在 QuartusII 中的時序并不是正式版的,要等Service Pack措施:只影响 Quartus 的 Waveform 7.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled措施:将setting中的timing Requirements&Option->More Timing setting->setting->

6、;Enable Clock Latency中的on改成OFF  8.Warning: Found clock high time violation at 14.8 ns on register"|counter|lpm_counter:count1_rtl_0|dffs11"原因:违反了steup/hold时间，应该是后仿真，看看波形设置是否和时钟沿符合steup/hold时间措施:在中间加个寄存器可能可以解决问题 9.warning: circuit may not operate.detected 46 non-operational paths

7、clocked by clock clk44 with clock skew larger than data delay原因:时钟抖动大于数据延时,当时钟很快，而if等类的层次过多就会出现这种问题,但这个问题多是在器件的最高频率中才会出现措施：setting->timing Requirements&Options->Default required fmax 改小一些，如改到50MHZ 10.Design contains <number> input pin(s) that do not drive logic原因:输入引脚没有驱动逻辑(驱动其他

8、引脚）,所有的输入引脚需要有输入逻辑措施:如果这种情况是故意的,无须理会,如果非故意,输入逻辑驱动. 11.Warning：Found clock high time violation at 8.9ns on node'TEST3.CLK'原因：FF中输入的PLS的保持时间过短措施：在FF中设置较高的时钟频率 12.Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks - node(s) analyzed as buffer(s)

9、 resulting in clock skew原因:如果你用的 CPLD 只有一组全局时钟时，用全局时钟分频产生的另一个时钟在布线中当作信号处理，不能保证低的时钟歪斜(SKEW)。会造成在这个时钟上工作的时序电路不可靠，甚至每次布线产生的问题都不一样。措施:如果用有两组以上全局时钟的 FPGA 芯片，可以把第二个全局时钟作为另一个时钟用，可以解决这个问题。 13.Critical Warning: Timing requirements were not met. See Report window for details.原因：时序要求未满足，措施：双击Compilation R

10、eport->Time Analyzer->红色部分（如clock setup:'clk'等）->左键单击list path,查看fmax的SLACK REPORT再根据提示解决,有可能是程序的算法问题  14.Can't achieve minimum setup and hold requirement <text> along<number> path(s). See Report window for details.原因：时序分析发现一定数量的路径违背了最小的建立和保持时间，与时钟歪斜有关,一般是由

11、于多时钟引起的措施：利用Compilation Report->Time Analyzer->红色部分（如clockhold:'clk'等），在slack中观察是hold time为负值还是setup time 为负值，然后在：Assignment->Assignment Editor->To中增加时钟名(fromnode finder)，Assignment Name中增加和多时钟有关的Multicycle 和Multicycle Hold选项，如hold time为负，可使Multicycle hold的值>multicycle,如设为2和1。

12、 15: Can't analyze file - file E:/quartusii/*/*.v is missing原因：试图编译一个不存在的文件，该文件可能被改名或者删除了措施：不管他，没什么影响 16.Warning: Can't find signal in vector source file for input pin|whole|clk10m原因：因为你的波形仿真文件（ vector source file ）中并没有把所有的输入信号(input pin)加进去，对于每一个输入都需要有激励源的  17.Warning: U

13、sing design file lpm_fifo0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: lpm_fifo0原因：模块不是在本项目生成的，而是直接copy了别的项目的原理图和源程序而生成的，而不是用QUARTUS将文件添加进本项目措施：无须理会，不影响使用 18.Timing characteristic

14、s of device <name> are preliminary原因：目前版本的QuartusII只对该器件提供初步的时序特征分析措施：如果坚持用目前的器件，无须理会该警告。关于进一步的时序特征分析会在后续版本的Quartus得到完善。 19.Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family原因：用analyze_latches_as_synchronous_elements

15、setting可以让Quaruts II来分析同步锁存，但目前的器件不支持这个特性措施：无须理会。时序分析可能将锁存器分析成回路。但并不一定分析正确。其后果可能会导致显示提醒用户：改变设计来消除锁 存器 20.Warning:Found xx output pins without output pin load capacitance assignment原因：没有给输出管教指定负载电容措施：该功能用于估算TCO和功耗，可以不理会，也可以在Assignment Editor中为相应的输出管脚指定负载电容，以消除警告 21.Warning: Found 6 node(s)

16、in clock paths which may be acting as ripple and/or gated clocks - node(s) analyzed as buffer(s) resulting in clock skew 原因：使用了行波时钟或门控时钟，把触发器的输出当时钟用就会报行波时钟，将组合逻辑的输出当时钟用就会报门控时钟措施：不要把触发器的输出当时钟，不要将组合逻辑的输出当时钟，如果本身如此设计，则无须理会该警告 22.Warning (10268): Verilog HDL information at lcd7106.v(63):Always

17、 Construct contains both blocking and non-blocking assignments原因： 一个always模块中同时有阻塞和非阻塞的赋值 23  Warning: Ignored node in vector source file. Can't find corresponding node name "class_sig2" in design. -没有编写testbench文件，或者没有编辑输入变量的值  testbench里是元件申明和映射24. Warning: Compil

18、er packed, optimized or synthesized away node "temp19". Ignored vector source file node.  -"temp19"被优化掉了 25. Warning: Design contains 2 input pin(s) that do not drive logic Warning: No output dependent on input pin "clk" Warning: No output dependent

19、on input pin "sign"  -输出信号与输入信号无关26. Warning: Ignored node in vector source file. Can't find corresponding node name "over" in design.-在源文件中找不到对应的节点“over”。27：Warning: No exact pin location assignment(s) for 16 pins of 16 total pins定义的管脚没有和外部的管脚连接.28：Warning: Ignored loca

20、tions or region assignments to the following nodesWarning: Node "78ledcom4" is assigned to location or region, but does not exist in design设计中没提到"78ledcom4" ，而分配了管脚给它。说明：有时候运行了TCL脚本文件后需要修改，修改后有一些先前分配的管脚不需要了，如果没有delete，则会出现此提示。解决办法：assignments->pins，把不用的管脚删除即可（TCL脚本文件里的多余管脚分配语句

21、最好也一起delete）。 (二) Quartus常见错误分析 1. Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated with formal port "class" of mode "out"-两者不能连接起来 2. Error: VHDL Interface Declaration error in clk_gen.vhd(29): int

22、erface object "clk_scan" of mode out cannot be read. Change object mode to buffer or inout.  -信号类型设置不对，out当作buffer来定义 3. Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen"  -引用的例化元件未定义实体entity "clk_gen"  4.  E

23、rror: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class" in design entity does not have std_logic_vector type that is specified for the same generic in the associated component  -在相关的元件里没有当前文件所定义的类型 5. Error: VHDL error at tongbu.vhd(16): can't infer regist

24、er for signal "gate" because signal does not hold its outside clock edge  6. Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binary operator "or" 7. Error: VHDL Association List error at period_counter.vhd(38): act

25、ual parameter assigned to formal parameter "alarm", but formal parameter is not declared-连接表错误，形参"alarm"赋值给实参，形参没定义，可能是形参与实参的位置颠倒了，规定形参在实参之前。 8. Error: Ignored construct behavier at period_counter.vhd(15) because of previous errors因为前一个错误而导致的错误 9. Error: VHDL error at p

26、eriod_counter.vhd(38): type of identifier "alarm" does not agree with its usage as std_logic type"alarm"的定义类型与使用的类型不一致 10.Error: VHDL error at shift_reg.vhd(24): can't synthesize logic for statement with conditions that test for the edges of multiple clocks  -同一进程中含

27、有两个或多个if(edge)条件，（一个进程中之能有一个时钟沿） 11. Error: Can't resolve multiple constant drivers for net "datain_reg22" at shift_reg.vhd(19) 12. Error:  can't infer register for signal "num0" because signal does not hold its outside clock edge 13. Error: Can't

28、elaborate top-level user hierarchy 14. Error: Error: Can't resolve multiple constant drivers for net "cs_in" at led_key.vhd(32)     -有两个以上赋值语句，不能确定“cs_in”的值，  15. Error: Can't access JTAG chain     无法找到下载链16. Error: Can't name logic scfifo0 of