数码管动态VHDL

1、动态数码管 library IEEE;entity count1000 isport(clock:in std_logic;clk:out std_logic;end entity count1000;architecture one of count1000 issignal q:std_logic;beginprocess(clockvariable a:integer range 0 to 10000;beginif clock'event and clock='1' thenif a=10000 thena:=0;q<= not q;elsea:=a+1;

2、end if;end if;end process;clk<=q;end architecture one;library IEEE;entity count8 isport(clk:in std_logic;a:buffer std_logic_vector(2 downto 0; end entity count8;architecture one of count8 isbeginprocess(clkbeginif clk'event and clk='1' thenif a=7 thena<="000"elsea<=a+1

3、;end if;end if;end process;end one;library IEEE;entity seg7 isport(clk:in std_logic;q:out std_logic_vector(6 downto 0;end entity seg7;architecture one of seg7 issignal w:std_logic_vector(3 downto 0:="0000" beginprocess(clkbeginif clk'event and clk='1' thenif w="1111"

4、thenw<="0000"elsew<=w+1;end if;end if;end process;process(wbegincase w iswhen "0000"=> q<="1111110"when "0001"=> q<="0110000"when "0010"=> q<="1101101"when "0011"=> q<="1111001"whe

5、n "0100"=> q<="0110011" when "0101"=> q<="1011011" when "0110"=> q<="1011111"when "0111"=> q<="1110000"when "1000"=> q<="1111111"when "1001"=> q<="11

6、11011"when "1010"=> q<="1110011"when "1011"=> q<="0011111"when "1100"=> q<="1001110"when "1101"=> q<="0111101"when "1110"=> q<="1001111"when others=> q<="1000111"end case;end process;end one;library IEEE;port(clock:in std_logic;clk:out std_logic;end entity count1HZ;architecture one of count1HZ is signal q:std_logic;beginprocess(clockvariable a:integer range 0 to 10000000; beginif clock'event and clock='1'