定时器PWM输出实验

1、定时器PWM输出实验1. 实验目的1) 熟悉Linux开发环境。2) 掌握S5PV210内部相关寄存器的操作方法，最终实现对外部设备的控制。3) 熟悉在Linux裸机环境下的C语言编程。4) 熟悉S5PV210的定时器编程。2 实验内容学习并编程实现ARM的定时器PWM输出。3 实验设备1) 硬件：S5PV210教学实验箱、PC机；2) 软件：PC机操作系统Windows 98(2000、XP) VMware workstation+Ubuntu12开发环境。4 基础知识S5PV210共有5个32bit的PWM定时器，其中定时器0、1、2、3有PWM功能，定时器4没有输出引脚。PWM定时器使用

2、PCLK_PSYS作为时钟源。时钟初始化相关寄存器定时器初始化相关定时器定时器PWM输出控制的相关内容：GPD0CON确定GPD0DAT引脚的功能，本实验用GPD00作为TOUT_0的输出。实验程序#define MP0_4CON(*(volatile unsigned long *)0xE0200340)#define MP0_4DAT(*(volatile unsigned long *)0xE0200344)#define GPD0CON (*(volatile unsigned long *)0xE02000A0)#define GPD0DAT (*(volatile unsigned

3、 long *)0xE02000A4)/ clock#define APLL_LOCK (*(volatile unsigned long *)0xE0100000)#define MPLL_LOCK (*(volatile unsigned long *)0xE0100008)#define APLL_CON0 (*(volatile unsigned long *)0xE0100100)#define APLL_CON1 (*(volatile unsigned long *)0xE0100104)#define MPLL_CON (*(volatile unsigned long *)0

4、xE0100108)#define CLK_SRC0 (*(volatile unsigned long *)0xE0100200)#define CLK_SRC1 (*(volatile unsigned long *)0xE0100204)#define CLK_SRC2 (*(volatile unsigned long *)0xE0100208)#define CLK_SRC3 (*(volatile unsigned long *)0xE010020c)#define CLK_SRC4 (*(volatile unsigned long *)0xE0100210)#define CL

5、K_SRC5 (*(volatile unsigned long *)0xE0100214)#define CLK_SRC6 (*(volatile unsigned long *)0xE0100218)#define CLK_SRC_MASK0 (*(volatile unsigned long *)0xE0100280)#define CLK_SRC_MASK1 (*(volatile unsigned long *)0xE0100284)#define CLK_DIV0 (*(volatile unsigned long *)0xE0100300)#define CLK_DIV1 (*(

6、volatile unsigned long *)0xE0100304)#define CLK_DIV2 (*(volatile unsigned long *)0xE0100308)#define CLK_DIV3 (*(volatile unsigned long *)0xE010030c)#define CLK_DIV4 (*(volatile unsigned long *)0xE0100310)#define CLK_DIV5 (*(volatile unsigned long *)0xE0100314)#define CLK_DIV6 (*(volatile unsigned lo

7、ng *)0xE0100318)#define CLK_DIV7 (*(volatile unsigned long *)0xE010031c)#define CLK_DIV0_MASK 0x7fffffff#define APLL_MDIV 0x7d#define APLL_PDIV 0x3#define APLL_SDIV 0x1#define MPLL_MDIV0x29b#define MPLL_PDIV0xc#define MPLL_SDIV0x1#define set_pll(mdiv, pdiv, sdiv) (131 | mdiv16 | pdiv8 | sdiv)#define

8、 APLL_VAL set_pll(APLL_MDIV,APLL_PDIV,APLL_SDIV)#define MPLL_VALset_pll(MPLL_MDIV,MPLL_PDIV,MPLL_SDIV)/ PWM CLOCK#defineTCFG0 ( *(volatile unsigned long *)0xE2500000)#defineTCFG1 ( *(volatile unsigned long *)0xE2500004)#defineTCON ( *(volatile unsigned long *)0xE2500008)#defineTCNTB0 ( *(volatile un

9、signed long *)0xE250000C)#defineTCMPB0 ( *(volatile unsigned long *)0xE2500010)#defineTCNTO0 ( *(volatile unsigned long *)0xE2500014)#defineTCNTB1 ( *(volatile unsigned long *)0xE2500018)#defineTCMPB1 ( *(volatile unsigned long *)0xE250001C)#defineTCNTO1 ( *(volatile unsigned long *)0xE2500020)#defi

10、neTCNTB2 ( *(volatile unsigned long *)0xE2500024)#defineTCMPB2 ( *(volatile unsigned long *)0xE2500028)#defineTCNTO2 ( *(volatile unsigned long *)0xE250002C)#defineTCNTB3 ( *(volatile unsigned long *)0xE2500030)#defineTCMPB3 ( *(volatile unsigned long *)0xE2500034)#defineTCNTO3 ( *(volatile unsigned

11、 long *)0xE2500038)#defineTCNTB4 ( *(volatile unsigned long *)0xE250003C)#defineTCNTO4 ( *(volatile unsigned long *)0xE2500040)#defineTINT_CSTAT ( *(volatile unsigned long *)0xE2500044)void init_clock(void) CLK_SRC0 = 0x0;/ close PLL APLL_LOCK= 0x0000FFFF; MPLL_LOCK = 0x0000FFFF; / set PLL APLL_CON0

12、 =APLL_VAL;/FOUT= MDIV * FIN / (PDIV*2(SDIV-1) = 1000 MHz MPLL_CON = MPLL_VAL;/ FOUT = MDIV*FIN/(PDIV*2SDIV)=667 MHz CLK_SRC0= 0x10001111;/ FOUT = MDIV*FIN/(PDIV*2SDIV)=667 MHzvoid init_timer(unsigned long tcntb,unsigned long tcmpb)TCON = 0;TCFG0= (TCFG0 & 0xff00ff)|0x41;/设置预分频系数65TCFG1 =(TCFG1 & (0

13、xf0)|0x04;/ 16分频 输入时钟= PCLK /(prescaler+ 1) /divider =62500hzTCNTB0 = tcntb;TCMPB0 = tcmpb;TCON |= 11;/ 更新TCNTB0 TCMPB0 TCON &= (11);/ 清手动更新位TCON |= (10)|(1 0;count-) for(i=0;i loop; i+) j+; void main(void) GPD0CON = (GPD0CON & (0xF 0)|0x2;/ 控制GPD00作为TOUT_0的输出 MP0_4CON= (MP0_4CON & 0xFFFF0000) | 0x11110000; MP0_4DAT|= 0xF0; init_clock();/初始化时钟 init_timer