用Verilog HDL编写的四路抢答器

1、四路抢答器设计Verilog HDL语言抢答器为四路，20秒倒计时，抢到后显示锁定，计时停止，若提前抢答会在另外数码管显示抢答号码。在BASYS 2 开发板上可以实现module qiang_da_qi(a_to_g,A_TO_D,clk,qiang_da,button,xuan );output wire 6:0a_to_g;output wire 3:0A_TO_D;input wire clk;/50MHz时钟wire 3:0qian;wire 3:0bai;wire 2:0shi;wire 2:0ge;wire cp;/1s时钟input wire 3:0qiang_da;input

2、button;wire suo_1;wire 2:0bian_ma_cun;wire fankui;output wire xuan;shumaguan shumaguan0(a_to_g,A_TO_D,clk,qian,bai,shi,ge);cp_1s cp_1s0(clk,cp);xuan_shou xuan_shou0(qiang_da,button,suo_1,bian_ma_cun,fankui);wei_xuan wei_xuan0(bian_ma_cun,xuan,shi,ge);fuwei_kongzhi fuwei_kongzhi0(button,xuan);jishu_k

3、ongzhi jishu_kongzhi0(bai,qian,cp,suo_1,xuan,fankui);endmodulemodule shumaguan(a_to_g,A_TO_D,clk,qian,bai,shi,ge);/数码管驱动output reg 6:0a_to_g;output reg 3:0A_TO_D;input wire clk;input wire 3:0qian;input wire 3:0bai;input wire 2:0shi;input wire 2:0ge;reg 3:0duan;reg 1:0wei;reg a;reg 16:0q;always(posed

4、ge clk)beginif(q=49999)beginq=0;a=a;endelseq=q+1;endalways(*)/7位段译码case(duan)0:a_to_g=7b0000001;1:a_to_g=7b1001111;2:a_to_g=7b0010010;3:a_to_g=7b0000110;4:a_to_g=7b1001100;5:a_to_g=7b0100100;6:a_to_g=7b0100000;7:a_to_g=7b0001111;8:a_to_g=7b0000000;9:a_to_g=7b0000100;default:a_to_g=7b0000001;endcasea

5、lways(*)/4位位选译码case(wei)3:beginA_TO_D=4b1110;duan=qian;end2:beginA_TO_D=4b1101;duan=bai;end1:beginA_TO_D=4b1011;duan=shi;end0:beginA_TO_D=4b0111;duan=ge;enddefault:A_TO_D=4b1110;endcasealways(posedge a)/四个状态循环if(wei=3)wei=0;elsewei=wei+1;endmodulemodule cp_1s(clk,a); /提供1秒脉冲input wire clk;output reg

6、 a;reg 25:0q;always(posedge clk) beginif(q=24999999)beginq=0;a=a;end elseq=q+1;endendmodulemodule xuan_shou(qiang_da,qing_ling,suo_1,bian_ma_cun,fankui);/选手抢答模块，某选手抢答后结果锁存input wire 3:0qiang_da;reg 2:0bian_ma;wire suo;input wire qing_ling;input wire fankui;output reg 2:0bian_ma_cun;output wire suo_1

7、; always(*)begincase(qiang_da)1:bian_ma=3b001;2:bian_ma=3b010;4:bian_ma=3b011;8:bian_ma=3b100;default:bian_ma=3b000;endcaseendassign suo=(bian_ma_cun0)&(bian_ma_cun1)&(bian_ma_cun2);assign suo_1=suo&fankui;always(*)beginif(qing_ling=1)bian_ma_cun=3b000;else if(suo_1=0)bian_ma_cun=bian_ma_cun;elsebia

8、n_ma_cun=bian_ma;endendmodulemodule wei_xuan(bian_ma_cun,xuan,bai,ge);/控制选手是否提前抢答模块input wire 2:0bian_ma_cun;input wire xuan;output reg 2:0bai;output reg 2:0ge;always(*)begincase(xuan)0:beginbai=bian_ma_cun;ge=3b000;end1:beginbai=3b000;ge=bian_ma_cun;enddefault:beginbai=3b000;ge=3b000;endendcaseende

9、ndmodulemodule fuwei_kongzhi(fu_wei,zong_kong);/复位与开始抢答的状态转换input wire fu_wei;output reg zong_kong;always(posedge fu_wei)beginzong_kong=zong_kong;endendmodulemodule jishu_kongzhi(q1,q2,clk,suo,clr,fankui);/计数电路及其控制模块output wire 3:0q1;output wire 3:0q2;input wire clk;input wire suo;input wire clr;out

10、put wire fankui;wire a;count20 count20_0(a,clr,q1,q2);assign fankui=(q10&q11&q12&q13&q20&q21&q22&q23);assign a=clr&suo&fankui&clk;endmodulemodule count20(a,clr,q1,q2); /计数器，从20计到0input wire a;input wire clr;output reg 3:0q1;output reg 3:0q2;always(posedge a or negedge clr)beginif(clr=0)beginq1=4b000

11、0;q2=4b0010;endelse if(q1=0)beginq2=q2-1;q1=9;endelseq1=q1-1;endendmodule在BASYS 2 开发板的管脚配置：NET A_TO_D3 LOC = F12;NET A_TO_D2 LOC = J12;NET A_TO_D1 LOC = M13;NET A_TO_D0 LOC = K14;NET a_to_g6 LOC = L14;NET a_to_g5 LOC = H12;NET a_to_g4 LOC = N14;NET a_to_g3 LOC = N11;NET a_to_g2 LOC = P12;NET a_to_g1 LOC = L13;NET a_to_g0 LOC = M12;NET qiang_da3 L