可编程逻辑器件课程设计实践报告

1、精选优质文档-倾情为你奉上信息工程专业2009级可编程逻辑器件及应用课程设计实践报告设计题目 交通灯控制器设计 专业班级_信息工程091_ 学 号_ 姓 名_ _ 完成时间_ 可编程逻辑器件及应用课程设计实践报告1.设计题目交通灯控制器的设计2.设计要求利用VHDL语言和原理图混合的方法设计一个设计一个由一条主干道和一条支干道的汇合点形成的十字交叉路口的交通灯控制器，具体要求如下：(1) 主、支干道各设有一个绿、黄、红指示灯，两个显示数码管。(2) 主干道处于常允许通行状态，而支干道有车来才允许通行。 (3) 当主、支道均有车时，两者交替允许通行，主干道每次放行45 s，支干道每次放行25 s

2、，在每次由亮绿灯变成亮红灯的转换过程中，要亮5 s的黄灯作为过渡，并进行减计时显示。 3.设计方案根据交通灯控制器功能设计要求，本系统可由以下6个模块组成：45S计时模块CNT45S；25S计时模块CNT25S；05S计时模块CNT05S；交通灯控制模块JTDKZ；显示子模块XSKZ；译码器模块YMQ。4.具体实现（根据不同的方法进行描述，给出具体实现步骤，包括程序）1.在D盘建立七个文件夹，JTDKZ、CNT45S、CNT25S、CNT05S、XSKZ、YMQ、JTDKZQSJ。2. 运行Quartus II 软件，选择File.New Project Wizard 菜单建立一个新工程。工程

3、名称及顶层文件名称为JTDKZ，器件设置对话框中选择EPM240T100C5 芯片，完成新工程的建立。 3. 选择File.New 菜单，创建VHDL 描述语言设计文件，打开文本编辑器界面。 4. 选择File.Save As 菜单，将创建的VHDL 设计文件保存为JTDKZ.VHD。5. 在文本编辑器界面中编写VHDL 程序，代码如下： -JTDKZ.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JTDKZ IS PORT(CLK,SM,SB:IN STD_LOGIC; MR,MY,MG,BR,BY,BG: OUT STD_LOGIC)

4、;END ENTITY JTDKZ;ARCHITECTURE ART OF JTDKZ IS TYPE STATE_TYPE IS(A,B,C,D); SIGNAL STATE: STATE_TYPE; BEGIN CNT:PROCESS(CLK) IS VARIABLE S:INTEGER RANGE 0 TO 45; VARIABLE CLR,EN:BIT; BEGIN IF(CLK'EVENT AND CLK='1')THEN IF CLR='0'THEN S:=0; ELSIF EN='0' THEN S:=S; ELSE S:=

5、S+1; END IF; CASE STATE IS WHEN A=>MR<='0' MY<='0' MG<='1' BR<='1' BY<='0' BG<='0' IF(SB AND SM)='1' THEN IF S=45 THEN STATE<=B; CLR:='0' EN:='0' ELSE STATE<=A; CLR:='1' EN:='1' END IF;

6、 ELSIF(SB AND (NOT SM)='1' THEN STATE<=B; CLR:='0' EN:='0' ELSE STATE<=A; CLR:='1' EN:='1' END IF; WHEN B=>MR<='0' MY<='1' MG<='0' BR<='1' BY<='0' BG<='0' IF S=5 THEN STATE<=C;CLR:=&

7、#39;0' EN:='0' ELSE STATE<=B; CLR:='1' EN:='1' END IF; WHEN C=>MR<='1' MY<='0' MG<='0' BR<='0' BY<='0' BG<='1' IF(SM AND SB)='1' THEN IF S=25 THEN STATE<=D; CLR:='0' EN:='0'

8、 ELSE STATE<=C; CLR:='1' EN:='1' END IF; ELSIF SB='0' THEN STATE<=D; CLR:='0' EN:='0' ELSE STATE<=C; CLR:='1' EN:='1' END IF; WHEN D=>MR<='1' MY<='0' MG<='0' BR<='0' BY<='1' BG&

9、lt;='0' IF S=5 THEN STATE<=A;CLR:='0' EN:='0' ELSE STATE<=D; CLR:='1' EN:='1' END IF; END CASE; END IF; END PROCESS CNT;END ARCHITECTURE ART; 6. 选择Tools.Compiler Tool 菜单，编译JTDKZ.VHD 源文件。（可选项：编译无误后建立仿真波形文件JTDKZ.VWF。选择Tools.Simulator Tool 菜单进行仿真）。选择File.Cr

10、eate/Update .Create Symbol File for Current File 菜单，为当前工程生成一个符号文件JTDKZ.BSF 文件。选择File.Close Project 菜单关闭工程JTDKZ。 重复上面的过程，建立CNT45S，最后为当前工程生成一个符号文件CNT45S.BSF 文件。-CNT45S.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT45S IS PORT(SB,CLK,EN45:IN STD_LOGIC; DOUT45M,DO

11、UT45B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY CNT45S;ARCHITECTURE ART OF CNT45S IS SIGNAL CNT6B: STD_LOGIC_VECTOR(5 DOWNTO 0); BEGIN PROCESS(SB,CLK,EN45) IS BEGIN IF SB='0'THEN CNT6B<=CNT6B-CNT6B-1; ELSIF(CLK'EVENT AND CLK= '1')THEN IF EN45='1'THEN CNT6B<=CNT6B+

12、1;ELSIF EN45='0'THEN CNT6B<=CNT6B-CNT6B-1; END IF; END IF; END PROCESS; PROCESS(CNT6B) IS BEGIN CASE CNT6B ISWHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<=&q

13、uot;" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" D

14、OUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<=""DOUT45B<=&q

15、uot;" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" W

16、HEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN "&q

17、uot;=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<=""WHEN ""=>DOUT

18、45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<=&quo

19、t;" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOU

20、T45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<=""WHEN ""=>DOUT45M<="" DOUT45B<=&quo

21、t;" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHE

22、N ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN ""=>DOUT45M<="" DOUT45B<="" WHEN "&quo

23、t;=>DOUT45M<="" DOUT45B<="" WHEN OTHERS=>DOUT45M<="" DOUT45B<=""END CASE; END PROCESS;END ARCHITECTURE ART;重复上面的过程，建立CNT25S，最后为当前工程生成一个符号文件CNT25S.BSF 文件。-CNT25S.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTIT

24、Y CNT25S IS PORT(SB,SM,CLK,EN25:IN STD_LOGIC; DOUT25M,DOUT25B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY CNT25S;ARCHITECTURE ART OF CNT25S IS SIGNAL CNT5B: STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN PROCESS(SB,SM,CLK,EN25) IS BEGIN IF SB='0' OR SM='0' THEN CNT5B<=CNT5B-CNT5B-1; ELSIF(CL

25、K'EVENT AND CLK= '1')THEN IF EN25='1' THEN CNT5B<=CNT5B+1; ELSIF EN25='0'THEN CNT5B<=CNT5B-CNT5B-1; END IF; END IF; END PROCESS; PROCESS(CNT5B) IS BEGIN CASE CNT5B ISWHEN "00000"=>DOUT25B<="" DOUT25M<="" WHEN "00001"=

26、>DOUT25B<="" DOUT25M<="" WHEN "00010"=>DOUT25B<="" DOUT25M<="" WHEN "00011"=>DOUT25B<="" DOUT25M<="" WHEN "00100"=>DOUT25B<="" DOUT25M<="" WHEN "0010

27、1"=>DOUT25B<="" DOUT25M<="" WHEN "00110"=>DOUT25B<="" DOUT25M<="" WHEN "00111"=>DOUT25B<="" DOUT25M<="" WHEN "01000"=>DOUT25B<="" DOUT25M<="" WHEN &q

28、uot;01001"=>DOUT25B<="" DOUT25M<="" WHEN "01010"=>DOUT25B<="" DOUT25M<="" WHEN "01011"=>DOUT25B<="" DOUT25M<="" WHEN "01100"=>DOUT25B<="" DOUT25M<=""

29、 WHEN "01101"=>DOUT25B<="" DOUT25M<="" WHEN "01110"=>DOUT25B<="" DOUT25M<="" WHEN "01111"=>DOUT25B<="" DOUT25M<="" WHEN "10000"=>DOUT25B<="" DOUT25M<=&quo

30、t;" WHEN "10001"=>DOUT25B<="" DOUT25M<="" WHEN "10010"=>DOUT25B<="" DOUT25M<="" WHEN "10011"=>DOUT25B<="" DOUT25M<="" WHEN "10100"=>DOUT25B<="" DOUT25M&

31、lt;="" WHEN "10101"=>DOUT25B<="" DOUT25M<="" WHEN "10110"=>DOUT25B<="" DOUT25M<="" WHEN "10111"=>DOUT25B<="" DOUT25M<="" WHEN "11000"=>DOUT25B<=""

32、DOUT25M<="" WHEN OTHERS=>DOUT25B<="" DOUT25M<="" END CASE; END PROCESS;END ARCHITECTURE ART;重复上面的过程，建立CNT05S，最后为当前工程生成一个符号文件CNT05S.BSF 文件。-CNT05S.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT05S IS PORT(CLK,EN05M,EN05

33、B:IN STD_LOGIC; DOUT5: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY CNT05S;ARCHITECTURE ART OF CNT05S IS SIGNAL CNT3B: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN PROCESS(CLK,EN05M,EN05B) IS BEGIN IF(CLK'EVENT AND CLK= '1')THEN IF EN05M='1' OR EN05B='1' THEN CNT3B<=CNT3B+1; ELS

34、E CNT3B<="000" END IF; END IF; END PROCESS;PROCESS(CNT3B) IS BEGIN CASE CNT3B IS WHEN "000"=>DOUT5<="" WHEN "001"=>DOUT5<="" WHEN "010"=>DOUT5<="" WHEN "011"=>DOUT5<="" WHEN "100

35、"=>DOUT5<="" WHEN OTHERS=>-DOUT5<="" END CASE; END PROCESS;END ARCHITECTURE ART;重复上面的过程，建立XSKZ，最后为当前工程生成一个符号文件XSKZ.BSF 文件。-XSKZ.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY XSKZ IS PORT(EN45,EN25,EN05M,EN05B:IN STD_LOGIC; AIN

36、45M,AIN45B: IN STD_LOGIC_VECTOR(7 DOWNTO 0); AIN25M,AIN25B,AIN05: IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUTM,DOUTB: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY XSKZ;ARCHITECTURE ART OF XSKZ IS BEGIN PROCESS(EN45,EN25,EN05M,EN05B) IS BEGIN IF EN45='1'THEN DOUTM<=AIN45M(7 DOWNTO 0); DOUTB<=A

37、IN45B(7 DOWNTO 0); ELSIF EN05M='1'THEN DOUTM<=AIN05(7 DOWNTO 0); DOUTB<=AIN05(7 DOWNTO 0); ELSIF EN25='1' THEN DOUTM<=AIN25M(7 DOWNTO 0); DOUTB<=AIN25B(7 DOWNTO 0); ELSIF EN05B='1'THEN DOUTM<=AIN05(7 DOWNTO 0); DOUTB<=AIN05(7 DOWNTO 0); END IF; END PROCESS;E

38、ND ARCHITECTURE ART;重复上面的过程，建立YMQ，最后为当前工程生成一个符号文件YMQ.BSF 文件。-YMQ.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY YMQ IS PORT(AIN4:IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT7: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END ENTITY YMQ;ARCHITECTURE ART OF YMQ IS BEGIN PROCESS(AIN4) IS BEGIN CASE AIN4 IS WHEN "0000"=>DOUT7<="" WHEN "0001"=>DOUT7<=&quo