VHDL语言实例参考模板

1、VHDL语言实例例1：设计一七段显示译码器，用它来驱动七段发光管LED显示十六进制数字0到9和字母A到F。LED显示数码管为共阳极。LIBRARY ieee;                                 USE ieee.std_logic_1164.all; 

2、0;   ENTITY HEX2LED IS                               PORT(              

3、60;                              HEX :IN std_logic_vector(3 DOWNTO 0);        LED : OUT std_logic_vector(6 TO 0)  &

4、#160;         );                                  END HEX2LED;       &

5、#160;                        图例1 七段显示译码器实体 ARCHITECTURE HEX2LED_arc OF HEX2LED IS      BEGIN           &#

6、160;                           - HEX-TO-SEVEN-SEGMENT DECODER              - SEGMENT ENCODING  

7、                       - 0                           &#

8、160;            - -                                     

9、0; - 5 | |1                                   - - <-6             &

10、#160;             - 4 | |2                                   

11、0;- -                                  - 3                &#

12、160;                      WITH HEX SELECT   LED<= "1111001" when "0001",                

13、;      "0100100" when "0010",                     "0110000" when "0011",          

14、60;           "0011001" when "0100",                     "0010010" when "0101",      

15、               "0000010" when "0110",                     "1111000" when "0111",    &

16、#160;                "0000000" when "1000",                      "0010000" when "1001

17、",                    "0001000" when "1010",                     "0000011&q

18、uot; when "1011",                      "1000110" when "1100",                 &#

19、160; "0100001" when "1101",                     "0000110" when "1110",               

20、     "0001110" when "1111",                     "1000000" when others;    2 / 15END HEX2LED_arc;      

21、60;    例2：设计一个八选一数据选择器1）s是通道选择信号,   d0,d1,d2,d3,d4,d5,d6,d7数据输入    out1是数据输出ENTITY sels IS PORT(d0,d1,d2,d3,d4,d5,d6,d7:IN BIT;          s :INTEGER RANGE 0 TO 7;          out1

22、 :OUT BIT);END sels;图例2（a)    八选一数据选择器实体ARCHITECTURE sels_arc OF sels ISBEGIN       WITH s SELECT              out1 <= d0 WHEN 0,          

23、60;   d1 WHEN 1,              d2 WHEN 2,              d3 WHEN 3,        d4 WHEN 4,        

24、       d5 WHEN 5,              d6 WHEN 6,              d7 WHEN 7;END sels_arc;2)A,B,C是通道选择信号,    I0,I1,I2,I3,I4,I5,I6,I7数据输入 

25、 Q是数据输出LIBRARY ieee; USE ieee.std_logic_1164.all;ENTITY mux8 ISPORT(I0,I1,I2,I3,I4,I5,I6,I7,A,B,C:IN std_logic;          Q :OUT std_logic);END mux8; 图例2（b)    八选一数据选择器实体ARCHITECTURE mux8_arc OF mux8 IS    SIGNAL sel :INTEGER ；BEGI

26、N    Q <= I0 AFTER 10 ns WHEN sel= 0 ELSE              I1 AFTER 10 ns WHEN sel= 1 ELSE              I2 AFTER 10 ns WHEN sel= 2 ELSE   

27、60;          I3 AFTER 10 ns WHEN sel= 3 ELSE              I4 AFTER 10 ns WHEN sel= 4 ELSE              I5 AFTER 10 ns WHEN se

28、l= 5 ELSE              I6 AFTER 10 ns WHEN sel= 6 ELSE              I7 AFTER 10 ns ;   sel <= 0 WHEN A= 0 AND B= 0 AND C= 0 ELSE     

29、;            1 WHEN A= 1 AND B= 0 AND C= 0 ELSE                 2 WHEN A= 0 AND B= 1 AND C= 0 ELSE           &

30、#160;     3 WHEN A= 1 AND B= 1 AND C= 0 ELSE                 4 WHEN A= 0 AND B= 0 AND C= 1 ELSE                 5 WHEN A

31、= 1 AND B= 0 AND C= 1 ELSE                 6 WHEN A= 0 AND B= 0 AND C= 1 ELSE                 7;END mux8_arc;     &

32、#160;  例3：设计一D触发器d是输入端，clk是时钟信号控制端，q是触发器的输出端。其程序如下：LIBRARY ieee; USE ieee.std_logic_1164.all;ENTITY reg IS   PORT(d,clk:IN BIT;        q:OUT BIT);END reg;图例3 D触发器实体ARCHITECTURE reg_arc OF reg IS  BEGIN    PROCESS  &

33、#160;   BEGIN        WAIT UNTIL clk= 1;        q <= d;    END PROCESS;  PROCESSEND reg_arc;        例4：设计一基本RS触发器r、s为触发器的输入信号，q、not_q为触发器的输出信号。LIBRARY ieee; U

34、SE ieee.std_logic_1164.all;ENTITY RSFF IS   PORT(r,s:IN BIT;        q,not_q:OUT BIT);END RSFF;图例4 基本RS触发器实体ARCHITECTURE RSFF_arc OF RSFF IS  BEGIN    PROCESS(r,s)      VARIABLE last_state:BIT:= 0;  &#

35、160;   BEGIN        ASSERT NOT(r= 1 AND s= 1)        REPORT “Both r AND s equal to 1”        SEVERITY error;        IF r= 0 AND s= 0 THEN  &

36、#160;        last_state:= last_state ;        ELSIF r= 1 AND s= 0 THEN           last_state:= 0;        ELSE - r= 0 AND s= 1   

37、60;       last_state:= 1;        END IF;    q <= last_state AFTER 10 ns;    not_q <= NOT(last_state) AFTER 20 ns;  END PROCESS;END RSFF_arc;当r和s同时等于1时，触发器处于不定状态。程序设计中设置了断言语句是为了判断r和s都等于1时，输出终端将显示

38、报告“Both r AND s equal to 1”，同时终止模拟过程，并显示错误的严重error，以便设计者调试和修正模块程序。从IF到END IF是条件语句，用到了可选项ELSIF和ELSE来判别RS触发器的其它三种情况。IF语句后面是一赋值语句，将IF语句中赋值的中间变量lsat_state经10 ns后送到q端。图8-12是RS触发器的逻辑电路图。       例5：设计一个带有异步清零、同步置数、使能控制的四位二进制计数器LIBRARY ieee;USE ieee.std_logic_1164.all;ENTIT

39、Y COUNT2 IS   PORT(A: IN INTEGER RANGE 0 TO 3;        CLK: IN STD_LOGIC;        CLR: IN STD_LOGIC;        EN: IN STD_LOGIC;        LD: IN STD_LOGIC;&#

40、160;       Cout: OUT INTEGER RANGE 0 TO 3        );END COUNT2;图例5   四位二进制计数器实体ARCHITECTURE COUNT2_arc OF COUNT2 IS  SIGNAL  SIG: INTEGER RANGE 0 TO 3;BEGIN  PROCESS (CLK, CLR)  BEGIN    IF CLR =

41、'0' THEN       SIG <= 0;    ELSIF (CLK'EVENT AND CLK = '1') THEN      IF LD = '1' THEN         SIG <= A;      ELSE   

42、;     IF EN = '1' THEN           SIG <= SIG + 1;        ELSE           SIG <= SIG;        END IF

43、;     END IF;   END IF;  END PROCESS;   Cout <= SIG;END COUNT2_arc     例6：设计一个存储容量为28×8的RAM。CS为RAM的片选信号，WR为RAM的写信号，RD为RAM读信号，ADR：八位地址信号，Din：八位数据输入线，Dout为八位数据输出线。library IEEE;use IEEE.std_logic_1164.all;use ieee.std_logic_u

44、nsigned.all;entity RAM is    port (WR: in STD_LOGIC;                 RD: in STD_LOGIC;                 ADR: in STD_LOGIC_VECTOR (7 down

45、to 0);                 CS: in STD_LOGIC;                 Din: in STD_LOGIC_VECTOR (7 downto 0);         

46、       Dout: out STD_LOGIC_VECTOR (7 downto 0)               );end RAM;图例6   RAM实体architecture RAM_arch of RAM is   subtype word is std_logic_vector(7 downto 0);   type memory

47、 is array (0 to 15)of word;   signal adr_in:integer range 0 to 15;   signal sram:memory;  begin       adr_in<=conv_integer(ADR);      process(wr)begin         if(wr'event an

48、d wr='1')then           if(cs='1'and wr='1')then              sram(adr_in)<=din after 2 ns;           end if

49、;         end if;      end process;      process(rd,cs)begin         if(rd='0'and cs='1')then          

50、dout<=sram(adr_in)after 3 ns;         else           dout<="ZZZZZZZZ"after 4 ns;         end if;      end process;end RAM_arch;&#

51、160;        例7：利用枚举类型设计一个状态机，用灯的颜色代表相应的状态名。library IEEE;use IEEE.std_logic_1164.all;ENTITY traffic_light IS    PORT ( sensor,clock :in std_logic;          red_light,green_light,yellow_light:out std_lo

52、gic          );end traffic_light;architecture abc of traffic_light is     type t_state is (red,green,yellow);     signal present_state,next_state:t_state;begin  process(present_state,sensor)  begin &#

53、160;  case present_state is    when green=>        next_state<=yellow;        red_light<='0'        green_light<='1'     &

54、#160;  yellow_light<='0'    when red=>        red_light<='1'        green_light<='0'        yellow_light<='0'   &

55、#160;    if(sensor='1')then          next_state<=green;        else          next_state<=red;        end if;

56、60;   when yellow=>          red_light<='0'          green_light<='0'          yellow_light<='1'