集成电路设计-08-子系统设计

1、EIS-Wuhan University1集成电路设计EIS-Wuhan University2Outlinen加法器n移位器n存储器qROMqRAMEIS-Wuhan University3A Generic Digital ProcessorMEMORYDATAPATHCONTROLINPUT-OUTPUTEIS-Wuhan University4Building Blocks for Digital ArchitecturesArithmetic unit- Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.

2、)Memory- RAM, ROM, Buffers, Shift registersControl- Finite state machine (PLA, random logic.)- CountersInterconnect- Switches- Arbiters- Bus EIS-Wuhan University5An Intel Microprocessor9-1 Mux9-1 Mux5-1 Mux2-1 Muxck1CARRYGENSUMGEN+ LU1000umbs0s1g64sumsumbLU : LogicalUnitSUMSELato Cachenode1REGItaniu

3、m has 6 integer execution units like thisEIS-Wuhan University6位片式Bit-Sliced DesignBit 3Bit 2Bit 1Bit 0RegisterAdderShifterMultiplexerControlData-InData-OutTile identical processing elementsEIS-Wuhan University7Bit-Sliced DatapathAdder stage 1WiringAdder stage 2WiringAdder stage 3Bit slice 0Bit slice

4、 2Bit slice 1Bit slice 63Sum SelectShifterMultiplexersLoopback BusFrom register files / Cache / BypassTo register files / CacheLoopback BusLoopback BusEIS-Wuhan University89-2 AddersEIS-Wuhan University9The 1-bit Binary Full-AdderqHow can we modify it easily to build an adder?qHow can we make it bet

5、ter (faster, lower power, smaller)?generategeneratepropagatepropagatepropagatepropagatekillkillcarry status1111101011011011000101110100101010000000SCoutCinBA1-bit Full Adder(FA)ABSCinCoutEIS-Wuhan University10The Binary AdderG = A&BP = A BK = !A & !B S = A B Cin= P Cin Cout = A&B | A&

6、;Cin | B&Cin = G | P&Cin EIS-Wuhan University11Define 3 new variable which ONLY depend on A, BGenerate (G) = ABPropagate (P) = A BDelete = A BEIS-Wuhan University12Worst case delay linear with the number of bitstd = O(N)tadder = (N-1)tcarry + tsumFAFAFAFAA0B0S0A1B1S1A2B2S2A3B3S3Ci,0Co,0(= Ci

7、,1)Co,1Co,2Co,3EIS-Wuhan University13Complimentary Static CMOS Full Adder28 TransistorsABBACiCiAXVDDVDDABCiBABVDDABCiCiABACiBCoVDDSEIS-Wuhan University14反相特性Inversion PropertyABSCoCiFAABSCoCiFA输入反相，输出也反相。输入反相，输出也反相。EIS-Wuhan University15A3FAFAFAEven cellOdd cellFAA0B0S0A1B1S1A2B2S2B3S3Ci,0Co,0Co,1Co

8、,3Co,2EIS-Wuhan University16VDDCiABBABAABKillGenerate1-Propagate0-PropagateVDDCiABCiCiBACiABBAVDDSCo24 transistorsEIS-Wuhan University17Mirror AdderStick DiagramCiABVDDGNDBCoA CiCoCiABSEIS-Wuhan University18Transmission Gate Full AdderABPCiVDDAAAVDDCiAPABVDDVDDCiCiCoSCiPPPPPSum GenerationCarry Gener

9、ationSetupEIS-Wuhan University19Manchester Carry ChainCoCiGiPiVDD Generate (G) = ABPropagate (P) = A BDelete = A BEIS-Wuhan University20Manchester Carry ChainG2 C3G3Ci,0P0G1VDD G0P1P2P3C3C2C1C0EIS-Wuhan University21Manchester Carry ChainPi + 1Gi + 1CiInverter/Sum RowPropagate/Generate RowPiGiCi - 1C

10、i + 1VDDGNDStick DiagramEIS-Wuhan University22FAFAFAFAP0G1P1G1P2G2P3G3Co,3Co,2Co,1Co,0Ci,0FAFAFAFAP0G1P1G1P2G2P3G3Co,2Co,1Co,0Ci,0Co,3MultiplexerBP=PoP1P2P3Idea: If (P0 and P1 and P2 and P3 = 1)then Co3 = Ci0, else “kill” or “generate”.EIS-Wuhan University23CinCout 可用于16、32、64bit的sum运算。 代价：10-20%EIS

11、-Wuhan University24tadder = tsetup + M tcarry + (N/M-1)tbypass + (M-1)tcarry + tsumCarrypropagationSetupBit 03SumM bitstsetuptsumCarrypropagationSetupBit 47SumtbypassCarrypropagationSetupBit 811SumCarrypropagationSetupBit 1215SumEIS-Wuhan University25Ntpripp le a dd erb y pa ss a dd er4 .8EIS-Wuhan

12、University26超前进位LookAhead加法器Co kf AkBkCo k1GkPkCo k1+=Co kGkPkGk1Pk1Co k2+=Co kGkPkGk1Pk1P1G0P0Ci 0+=Expanding Lookahead equations:All the way:EIS-Wuhan University27AN-1, BN-1A1, B1P1S1 SN-1PN-1Ci, N-1S0P0Ci,0Ci,1A0, B0EIS-Wuhan University28Look-Ahead: TopologyCo,3Ci,0VDDP0P1P2P3G0G1G2G3EIS-Wuhan Un

13、iversity29Logarithmic Look-Ahead AdderA7FA6A5A4A3A2A1A0A0A1A2A3A4A5A6A7Ftp log2(N)tp NEIS-Wuhan University30Carry Lookahead TreesCo 0G0P0Ci 0+=Co 1G1P1G0P1P0Ci 0+=Co 2G2P2G1P2P1G0P+2P1P0Ci 0+=G2P2G1+=P2P1 G0P0Ci 0+G2:1P2:1Co 0+=Can continue building the tree hierarchically.EIS-Wuhan University31AiAi

14、-1BiBi-1RightLeftnopBit-Slice i.EIS-Wuhan University32桶形移位器The Barrel ShifterArea Dominated by WiringSh3Sh2Sh1Sh0Sh3Sh2Sh1A3A2A1A0B3B2B1B0: Control Wire: Data WireEIS-Wuhan University33对数移位器Logarithmic Shifter分级实现Sh1 Sh1Sh2 Sh2Sh4 Sh4A3A2A1A0B1B0B2B3EIS-Wuhan University349-4 存储器nMemory Classificatio

15、nnMemory ArchitecturesnThe Memory CoreqROMnEPROMnEEPROMnFLASHqRAMnSRAMnDRAMEIS-Wuhan University35Semiconductor Memory ClassificationEIS-Wuhan University36Memory Timing: DefinitionsReadRead CycleRead AccessRead AccessWriteWrite CycleDataWrite SetupData ValidWrite HoldEIS-Wuhan University37Memory Arch

16、itecture: DecodersWord 0Word 1Word 2WordN-2WordN-1StoragecellM bitsM bitsN wordsS0S1S2SN-2A0A1AK-1K=log2NSN-1Word 0Word 1Word 2WordN-2WordN-1StoragecellS0Input-Output(M bits)直接实现直接实现N x M memoryN words = N select signalsK = log2NDecoder reduces the number of select signalsInput-Output(M bits)Decoder

17、译码器EIS-Wuhan University38Array-Structured Memory ArchitectureA0Row DecoderA1Aj-1Sense Amplifiersbit lineword linestorage (RAM) cellAjAj+1Ak-1Read/Write CircuitsColumn Decoderamplifies bit line swingselects appropriate word from memory rowEIS-Wuhan University39Hierarchical Memory ArchitectureGlobalam

18、plifi e r / d riv erControlcircuit r yGlobal d a t a bu sBlock s e l e c torBlock 0RowaddressColumnaddressBlockaddressBlockiBlockP2 1I/OEIS-Wuhan University40Read-Only Memory CellsWord LineBit LineWLBL1WLBLWLBLWLBL0VDDWLBLGNDDiode ROMMOS ROM 1MOS ROM 2EIS-Wuhan University41EIS-Wuhan University42WL0G

19、NDBL0WL1WL2WL3VDDBL1Pull-up devicesBL2BL3GNDEIS-Wuhan University43All word lines high by default with exception of selected rowWL0WL1WL2WL3VDDPull-up devicesBL3BL2BL1BL0无电源线无电源线串联结构串联结构减少布线减少布线EIS-Wuhan University44Equivalent Transient Model for MOS NOR ROMnWord line parasiticsqWire capacitance and

20、gate capacitanceqWire resistance (polysilicon)nBit line parasiticsqResistance not dominant (metal)qDrain and Gate-Drain capacitanceVDDCbitrwordcwordWLBLEIS-Wuhan University45Decreasing Word Line DelayMetal bypassPolysilicon word lineK cellsPolysilicon word lineWLDriver(b) Using a metal bypass(a) Dri

21、ving the word line from both sidesMetal word lineWLEIS-Wuhan University46Precharged MOS NOR ROMWL 0GNDBL 0WL 1WL 2WL 3VDDBL 1Precharge devicesBL 2BL 3GNDprefEIS-Wuhan University47Floating gateSourceSubstrateGateDrainn+n+_ptoxtoxDevice cross-sectionSchematic symbolGSDAAvalanche injectionEIS-Wuhan Uni

22、versity48Floating-Gate Transistor Programming0 V-5 V0 VDSRemoving programming voltage leaves charge trapped5 V-2.5 V5 VDSProgramming results in higher VT.20 V10 V 5 V20 VDS雪崩注入雪崩注入Avalanche injectionEIS-Wuhan University49A “Programmable-Threshold” Transistor“ 0”-state“ 1”-stateDVTVWLVGS“ON”“OFF”ID 浮

23、栅上存储了电荷后，使开启电压提高到浮栅上存储了电荷后，使开启电压提高到7V左右，左右， 5V栅源电压下，晶体管不工作。栅源电压下，晶体管不工作。EIS-Wuhan University50WLBLVDD2 transistor cell 集成度低集成度低被编程后，浮栅被编程后，浮栅MOS管具有管具有较高的开启电压，施加正常的较高的开启电压，施加正常的VDD将处于关闭状态；将处于关闭状态；未被编程的浮栅未被编程的浮栅MOS等同于等同于正常正常MOS，处于导通状态。，处于导通状态。EIS-Wuhan University51Flash EEPROMControl gate擦除擦除erasurep-

24、substrateFloating gate薄隧道氧化层Thin tunneling oxiden+sourcen+drain编程编程programmingEIS-Wuhan University52SD12 VGcellarrayBL0BL1openopenWL0WL10 V0 V12 VEIS-Wuhan University53SD12 V6 VGBL0BL16 V 0 VWL0WL112 V0 V0 VEIS-Wuhan University545 V1 VGSDBL0BL11 V 0 VWL0WL15 V0 V0 VEIS-Wuhan University55NAND Flash M

25、emoryUnit CellWord line(poly)Source line(Diff. Layer)EIS-Wuhan University56NAND Flash MemoryWord linesSelect transistorBit line contactSource line contactActive areaSTICourtesy ToshibaEIS-Wuhan University57Characteristics of NVMEIS-Wuhan University58q STATIC (SRAM)qData stored as long as supply is a

26、ppliedqLarge (6 transistors/cell)qFastqDifferentialq DYNAMIC (DRAM)qPeriodic refresh requiredqSmall (1-3 transistors/cell)qSlowerqSingle EndedEIS-Wuhan University59WLBLVDDM5M6M4M1M2M3BLQQEIS-Wuhan University60CMOS SRAM Analysis (Read)WLBLVDDM5M6M4M1VDDVDDVDDBLQ= 1Q= 0CbitCbit预充电至预充电至VDDEIS-Wuhan Uni

27、versity61CMOS SRAM Analysis (Read)000.811.20.5Voltage rise V11.2 1.52Cell Ratio (CR)2.53Voltage Rise (V)Q选择合适的选择合适的CR，防止影响存储的信息。，防止影响存储的信息。EIS-Wuhan University62BL= 1BL= 0Q= 0Q= 1M1M4M5M6VDDVDDWLQ：10EIS-Wuhan University63PR=(W4/L4) / (W6/L6)EIS-Wuhan University646T-SRAM Layout VDDGNDQQWLBLB

28、LM1M3M4M2M5M6EIS-Wuhan University65Resistance-load SRAM CellStatic power dissipation - Want RL largeBit lines precharged to VDD to address tp problemM3RLRLVDDWLQQM1M2M4BLBLEIS-Wuhan University663-Transistor DRAM Cell No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = VWWL-VTnWWLBL1M1XM3M2CSBL2RWLVDDVDD-VTVVDD-VTBL2BL1XRWLWWLBL2预充电至预充电至VDD或或VDD-VtEIS-Wuhan University671-Transistor DRAM CellWrite: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line a