数电数字逻辑7

1、There are memory devices in the circuits;the output rely on both inputs and states !Chapter 7Sequential logic design principlesBasic memory devicesLatch: the inputs be watched continuously and output may be changed at any time independent of the clock;Flip-flop:the input be sampled and output may be

2、 changed only at the times determined by the clock !Bistable elementA positive feedback circuit made by two inverters.State (Q) can be hold, but cannot be set ! S-R latchwhen both S and R is (00), the state hold ! When SR=(10) Set: set Q = 1When SR=(01) Reset: set Q = 0Use NOR gates instead inverter

3、s: get two inputsThe time delay in S-R latchWe need time to setup a stable state !Initial state:Q=0Last state:Q=1If input from 11 to 00 The input (11) should be avoided !Initial state:Q=0 QN=0Last state:Q=? QN=?MetastableIf input signal is too short Initial state:Q=0Last state : metastableS-R latchW

4、hen inputs pulse is too short : metastable !Minimum-pulse-width tpw(min) : input hold time to avoid metastable !S-R latchUse NAND gates :When S=R=1 , both outputs are 1, but not complementary !S-R latch with enableUse AND gates to control the inputsWhen C=1, it is a normal S-R latch;When C=0, both i

5、nputs are cut off , and the state is hold !S-R latch with enableThe input pulse may be cut off by control signal !Hold time: after the change of C 01 ;Setup time: before the change of C 10 .How to avoid the metastableThe metastable is only happened when SR=00 !If we set S=1 or R=1 for enough time , the metastable will be ended!D latchTo avoid the inputs SR=11 and 00, S and R is made complement !When C=1, Q=D; when C=0, state hold ! The state is decided by the input Directly ! The time behavior of D latch when C=1 , the metastable will never happen !Only setup time shou