数电数字逻辑8

1、Shift register counters Feedback logic: a combinational logic input: Q; output: DShift register: a sequential logic Q(i)*=Q(i-1); Q(0)*=D Shift register Analyze for the 4-bit shift register Shift register counters Feedback logic: Q0* = Q3 4 states ring counter Connected as a left-shift register; Shi

2、ft register counters Feedback logic: Q0* = Q3 4 states ring counter 1-out-of-m coding deviceN flip-flops: N statesShift register counters 4 states ring counter Many invalid state circles:Not robust !Shift register counters 4 states ring counter: self-correcting Shift register counters Johnson counte

3、rFeedback logic:N flip-flop: 2N statesShift register counters Johnson counterAt any trigger time, only one output change :No glitches !The duty cycle for any output port is 50%!Shift register counters Self-correcting Johnson counterWhen Q3Q0=00load 0001 Shift register counters Linear feedback shift

4、register(LFSR) counters(Maximum-length sequence generator)N flip-flop: 2N-1 states (without “all 0” state)Shift register counters LFSR counter example: 3 bits Shift register counters LFSR counters : modified to include “0” stateShift register counters Design for periodic sequence generator 001101 001001101 011001101 110001101 101001101 010001101 100Output state analyze Use 3 bits shift registerFeedback logic:Shift register counters Design for periodic sequence generator 001010 001001010 010001010 101001010 010001010 100001010 000Output state analyze Must use 4 bits shif