VLSI超大规模集成电路：Arithmetic Circuits

ArithmeticCircuitsGenericDigitalProcessormemoryCPUPCaddressdataIRADDr5,r1,r3200200ADDr5,r1,r3MemorysystemCPUfetchesdata,instructionsfromamemoryhierarchy:MainmemoryL2cacheL1cacheCPUCachesandCPUsCPUcachecontrollercachemainmemorydatadataaddressdataaddressTheInstructionPipelineFETCHDECODEEXECUTEInstructionfetchedfrommemoryDecodingofregistersusedininstructionRegister(s)readfromRegisterBankShiftandALUoperationWriteregister(s)backtoRegisterBankPC-8 PC-4PC-4 PC-2PC PCARM ThumbARM7TDMCoreRegisterBankMultiplierAddressIncrementerALUBAVectorsA[31:0]AddressRegisterBarrelShifterPCALUReadDataRegisterWriteDataRegisterD[31:0]InstructionDecodeBuildingBlocksCPUArithmeticunit-

Bit-sliceddatapath(adder,multiplier,shifter,comparator,etc.)Memory-RAM,ROM,Buffers,Shiftregisters,registerfileControl-Finitestatemachine(PLA,randomlogic.)-CountersBit-SlicedDesignQuizWhywemustlearnthese?Memory:constructedwithregistersAdder:constructedwithcombinationallogicShiter:constructedwithcombinationallogic.So,why?AdderFull-AdderP、G,DDefine3newvariablewhichONLYdependonA,BGenerate(G)=ABPropagate(P)=A^BDelete=A

BNote:C0=G+PCi=G+(A+B)CiHSPICEDEMOTheRipple-CarryAdderWorstcasedelaylinearwiththenumberofbitsGoal:Makethefastestpossiblecarrypathcircuittd=O(N)tadder=(N-1)tcarry+tsumComplimentaryStaticCMOSFullAdder28Transistors？InversionPropertyMinimizeCriticalPathExploitInversionPropertyABetterStructure:TheMirrorAdderCarry-BypassAdderAlsocalled

Carry-SkipCarry-BypassAdder(cont.)tadder=tsetup+Mtcarry+(N/M-1)tbypass+(M-1)tcarry+tsumCarryRippleversusCarryBypassCarry-SelectAdderCarrySelectAdder:CriticalPathLinearCarrySelectSquareRootCarrySelectAdderDelays-ComparisonQuiz-FullAdder？ShifterTheBinaryShifterTheBarrelShifterAreaDominatedbyWiring4x4barrelshifterWidthbarrel~2pmMShifterwithStdcellShifterwithStdcellROMRead-OnlyMemoryCellsWLBL1WLBLWLBL0VDDWLBLGNDMOSROM1MOSROM2MOSORROMWL[0]VDDBL[0]WL[1]WL[2]WL[3]VbiasBL[1]Pull-downloadsBL[2]BL[3]VDDMOSNORROMWL[0]GNDBL[0]WL[1]WL[2]WL[3]VDDBL[1]Pull-updevicesBL[2]BL[3]GNDMOSNANDROMAllwordlineshighbydefaultwithexceptionofselectedrowWL[0]WL[1]WL[2]WL[3]VDDPull-updevicesBL[3]BL[2]BL[1]BL[0]SRAMMemoryArchitectureWord0Word1Word2WordN22WordN21StoragecellMbitsMbitsNwordsS0S1S2SN22A0A1AK21K5log2NSN21Word0Word1Word2WordN22WordN21StoragecellS0Input-Output(Mbits)IntuitivearchitectureforNxMmemoryToomanyselectsignals:Nwords==NselectsignalsK=log2NDecoderreducesthenumberofselectsignalsInput-Output(Mbits)DecoderArray-StructuredMemoryArchitectureAmplifyswingtorail-to-railamplitudeSelectsappropriateword6-transistorCMOSSRAMCellWLBLVDDM5M6M4M1M2M3BLQQHowtoholddata?WhyneedBLHowtowriteandread?CMOSSRAMAnalysis(Read)WLBLVDDM5M6M4M1VDDVDDVDDBLQ=1Q=0CbitCbitCMOSSRAMAnalysis(Read)000.20.40.60.811.20.5Voltagerise[V]11.21.52CellRatio(CR)2.53VoltageRise(V)CMOSSRAMAnalysis(Write)BL=1BL=0Q=0Q=1M1M4M5M6VDDVDDWLCMOSSRAMAnalysis(Write)6T-SRAM—LayoutVDDGNDQQWLBLBLM1M3M4M2M5M6RowDecodersWi=0;Case({A9,A8,A7…A0})begin…..i:Wi=1;…...endHierarchicalDecoders••••••A2A2A2A3WL0A2A3A2A3A2A3A3A3A0A0A0A1A0A1A0A1A0A1A1A1WL1Multi-stageimplementationimprovesperformanceDynamicDecodersPrechargedevicesVDDfGNDWL3WL2WL1WL0A0A0GNDA1A1fWL3A0A0A1A1WL2WL1WL0VDDVDDVDDVDD2-inputNORdecoder2-inputNANDdecoderSenseAmplifierstpCDV×Iav----------------=makeDVassmallaspossiblesmalllargeIdea:UseSenseAmpliferoutputinp