计算机组成与结构：chapter12 CPU Structure and Function

ComputerOrganization&ArchitectureChapter12

CPUStructureandFunction12.1ProcessororganizationStepsofCPUexecutingtheinstruction:FetchinstructionsInterpretinstructions/decodinginstructionsFetchdataProcessdataWritedataTodothesethings,CPUmustcontainALU,CUAlso,CPUneedstostoresomedatatemporarilyincludingthelocationofnextinstruction.Thus,CPUneedsasmallinternalmemory--registers

CPUWithSystemsBusInternalStructureofTheCPU12.2RegisterOrganizationDef.:workingspacefortemporarystorageinCPUNumberandfunctionvarybetweenprocessordesignsOneofthemajordesigndecisionsLocatedintoplevelofmemoryhierarchyTheregistersintheCPUservetwofunctions:User-visibleregistersProgrammercanusetheseregisterstoreduceaccessingmainmemoryControlandstatusregistersUsedbyCUandprivilegedprogram(OS)tocontroltheexecutionofuser’programsUserVisibleRegisters

Wemaycharacterizeuservisibleregistersasfourcategories:GeneralPurposeDataAddressConditionCodesGeneralPurposeRegistersMaybetruegeneralpurposeMayberestrictedTheremaybededicatedregistersforfloating-pointandstackoperationsMaybeusedfordataoraddressingDataAccumulatorAddressingSegmentpointers,indexregister,stackpointersDesignissuesconsiderationsofRegistersMakethemgeneralpurposeIncreaseflexibilityandprogrammeroptionsIncreaseinstructionsize&complexityMakethemspecializedSmaller(faster)instructionsPop,PushLessflexibilityHowManyRegisters?Between8–32Fewer=>morememoryreferencesMoredoesnotnoticeablyreducememoryreferencesandtakesupprocessorrealestateInsomeRISCsystem,hundredsofregistersisexhibitedHowlongshouldaregisterbe?LargeenoughtoholdthelargestaddressLargeenoughtoholdvaluesofmostdatatypesOftenpossibletocombinetwodataregistersCprogrammingdoubleinta;longinta;ConditionCodeRegistersBitssetbyCPUhardwareastheresultoflastoperationsCOAPZSPositive,negative,zero,overflow,etc,Aftertheresultoflastoperationsarestored,aconditioncodeisalsosetandthiscodemaybeusedforconditionbranchCanberead(implicitly)byprogramse.g.JumpifzeroCannot(usually)besetbyprogramsPartiallyvisibletoprogrammersControl&StatusRegistersThereareavarietyofregistersthatareemployedtocontroloperationoftheCPUMostareinvisibletoprogrammersFoursortsofregistersforinstructionexecutionProgramCounter(PC)InstructionRegister(IR)Thefetchedinstruction,fordecodingMemoryAddressRegister(MAR)address,connectedtoaddressbusMemoryBufferRegister(MBR)Data,connectedtodatabusProgramStatusWord—PSWAsetofbits,Includesthefollowingfieldsorflags:ConditionCodesSignoflastresultZero:Setwhentheresultis0CarrysetwhenoperationresultedinacarryorborrowEqual:setwhenalogicalcompareresultisequalityOverflow:usedtoindicatearithmeticoverflowInterruptenable/disableallowornotallowainterruptSupervisorindicateswhethertheCPUisexecutinginsupervisororusermodeSupervisorModeIntelringzeroKernelmodeAllowsprivilegedinstructionstoexecuteUsedbyoperatingsystemNotavailabletouserprogramsOtherRegistersMayhaveregisterspointingto:Processcontrolblocks(seeO/S)InterruptVectors(seeO/S)StackPagetableSegmenttableControlofI/OoperationsTwofactorsconsideredindesigningcontrolregisterOSsupportingCPUdesignandoperatingsystemdesignarecloselylinked,theyshouldmatcheachotherControlinformationallocatedinmemoryandregistersControlinformationmaybestoredinthefirstfewhundredwordsofmainmemoryalso,designermustdecidehowmuchisinregistersandhowmuchinmemory—trade-offExampleforRegisterOrganizationsMC6800RegistersMotoralageneralpurposeregisters832-bitdataregisters932-bitaddressregistersThewidthoftheregisterallows8,16,32-bitdataoperations,determinedbyopcodeA7usedforusersandA7’usedforOSA32-bitPCand16-bitstatusregister8086RegistersSpecialregisters416-bitdataregisters416-bitpointer&indexregisters416-bitsegmentregisterscanbeusedin8-bitmodeAh,Al

Aninstructionpointer--PC,16bitAsetof1-bitstatusandcontrolflags80386~PIIRegistersAnextensionof808632-bitsregistersUpwardcompatibility12.3InstructionCycleReviewIndirectAddressingCycleMayrequirememoryaccesstofetchoperandsIndirectaddressingrequiresmorememoryaccessesCanbethoughtofasadditionalinstructionsub-cycleInstructionCyclewithIndirect

InstructionCycleStateDiagramDataFlow(InstructionFetch)DependsonCPUdesign,ingeneral:FetchPCcontainsaddressofnextinstructionAddressmovedtoMARAddressplacedonaddressbusControlunitrequestsmemoryreadResultplacedondatabus,copiedtoMBR,thentoIRMeanwhilePCincrementedby1DataFlow--FetchCycleDiagramDataFlow(IndirectFetch)IRisexaminedIfindirectaddressing,indirectcycleisperformedRightmostNbitsofMBRtransferredtoMARControlunitrequestsmemoryreadResult(addressofoperand)movedtoMBRMBRIRDataFlow--IndirectDiagramDataFlow(Execute)NofixedformsDependsoninstructionbeingexecutedMayincludeMemoryread/writeInput/OutputRegistertransfersALUoperationsDataFlow(Interrupt)SimpleandpredictableCurrentPCsavedtoallowresumptionafterinterruptContentsofPCcopiedtoMBRSpecialmemorylocation(e.g.stackpointer)loadedtoMARMBRwrittentomemoryPCloadedwithaddressofinterrupthandlingroutineNextinstruction(firstinstructionofinterrupthandler)canbefetchedDataFlow--InterruptDiagram12.4InstructionpipeliningPre-fetchFetchaccessesmainmemoryExecutionusuallydoesnotaccessmainmemoryCanfetchnextinstructionduringdecodingandexecutionofcurrentinstructionCalledinstructionpre-fetchPerformancemaybeImprovedbyPre-fetchPre-fetchcanimprovespeedofprogramexecutionButnotdoubled:Anyjumporbranchmeansthatpre-fetchedinstructionsarenottherequiredinstructionsAddmorestagestoimproveperformance

TwoStageInstructionPipelineIntroductiontoInstructionPipeliningInadditiontofastercircuitry,organizationenhancementtoCPUcanimprovecomputerperformanceRegisters,cache,etcAnotherorganizationalapproachispipeliningInstructionpipelining

issimilartotheassemblylineinthefactoryLaundryexample:

Ann,Brian,Cathy,Dave

eachhaveoneloadof

clothestowash,dry,

andfold Washertakes30minutes Dryertakes40minutes “Folder”takes20minutesABCDSequentialLaundryPipelinedLaundryDoesn’thelplatencyofsingletask,butthroughputofentirePipelineratelimitedbysloweststageMultipletasksworkingatsametimeusingdifferentresourcesUnbalancedstagelength

reducethespeedofpipelineStallfordependencesPipelining

Infact,aninstructionhasanumberofstages:Fetchinstruction(FI)Decodeinstruction(DI)Calculateoperandsaddress(CO)Fetchoperands(FO)Executeinstructions(EI)Writeoperand(WO)Thevariousstageswillbenearlyequalduration,wecanoverlaptheseoperationsTimingDiagramfor

InstructionPipelineOperationSpecificationsInFig.12.10,eachinstructiongoesthroughallsixstagesofthepipeline.Thiswillnotalwaysbethecase,sosomenulloperationsexistE.gLOADinstructionItisassumedthatnoconflictsanddependenciesoccurIfthesixstagesarenotofequalduration,shortstagesmustwaitConditionalbranchandinterruptwillreducetheperformanceofpipelineTheEffectofaConditionalBranchonInstructionPipelineOperationSixStageInstructionPipelineAlternativePipelineDepictionQuestion:themorestagesinthepipeline,thefastertheexecutionrate?Answer:itisunlikely,becauseAteachstage,thereissomeoverheadinvolvedinmovingdatafrombuffertobufferandinperformingvariouspreparationanddeliveryfunction,lengthenthetotalexecutiontimeofasingleinstructionThemorestages,themorecomplexcontrollogiccircuitsPipelinePerformanceThecycletimeofaninstructionpipelineInstructiongoesastageinpipeline,theneededtime:d:delayofalatch,d<<maxSupposethatninstructionsareprocessed,withnobranchesandinterrupt.Thetotaltimetoexecuteallninstructions:Tk=[k+(n-1)]

SpeedupFactor:Speedup~nRelationshipSpeedup~nRelationshipThroughputrate(Tp):DealingwithBranchesMultipleStreamsPre-fetchBranchTargetLoopbufferBranchpredictionDelayedbranchingMultipleStreamsHavetwopipelinesPre-fetcheachbranchintoaseparatepipelineUseappropriatepipelineLimitsLeadstobus®istercontentionMultiplebranchesleadtofurtherpipelinesbeingneededUsedbyIBM370,3033Pre-fetchBranchTargetTargetofbranchispre-fetchedinadditiontoinstructionsfollowingbranchKeeptargetuntilbranchisexecutedUsedbyIBM360/91LoopBufferAsmall,veryfastmemorycontainingnmostrecentlyfetchedinsequenceinstructionsMaintainedbyfetchstageofpipelineIfabranchistobetaken,thehardwarefirstchecksbufferbeforefetchingfrommemoryVerygoodforsmallloopsc.f.cache,differenceinsmallerinsizeandonlyretainsinstructionsinsequenceUsedbyCRAY-1

LoopBufferDiagramBranchPredictionPredictnevertakenAssumethatjumpwillnothappenAlwaysfetchnextinstructionVAX11/780VAXwillnotpre-fetchafterbranchifapagefaultwouldresultPredictalwaystakenAssumethatjumpwillhappenAlwaysfetchtargetinstructionIfapagefaultoccurs,waituntilthebranchinstructioniscompletedPredictbyOpcodeSomeinstructionsaremorelikelytoresultinajumpthanothersCangetupto75%successTaken/NottakenswitchBasedonprevioushistoryBits(1~2bits)GoodforloopsanditerationsBranchHistoryTable/BranchTargetBufferAsmallcacheBTB/BHTEachentryconsistsof3parts:(seepp438Fig.12.18)BranchinstructionaddressTargetaddressHistorystateinformationBranchPredictionStateDiagramBranchPredictionFlowChartPredictNeverTakenStrategyBranchHistoryTableDelayedBranchInsertNULLoperationsStallthepipeliningUsedinearlyCPURearrangeinstructionsOut-of-orderexecutionUsednow80486Instructionpipeline

Five-stagespipeline:FetchTwo16Bpre-fetchbuffersOnaverage,eachcanstore5instructionspre-fetchedDecodestage1OpcodeandaddressingmodeisdecodedDecodestage2ExpandopcodeintocontrolsignalfortheALUComputethemorecomplexaddressingmodesExecutionWriteback80486Instructionpipelineexamples12.5ThePentiumProcessorRegisterOrganizationIntegerUnitFloating-pointUnitforRegisterOrganizationEFLAGSRegisterSpecificationTrapflag(TF)Whenset,interruptafteraninstructionexecution,usedfordebugInterruptenableflag(IF)RecognizeexternalinterruptDirectionflag(DF)IncrementordecrementinstringprocessingSIorDII/Oprivilegeflag(IOPL)Whenset,forbidaccessingI/OdevicesResumeflag(RF)RestarttheinstructionwhenadebugexceptionoccursAlignmentcheck(AC)ActivateswhenaddressingonaboundaryofwordanddoublewordVirtualmode(VM)Pentiumto8086ornotIdentificationflag(ID)UsedfortestingCPUIDVirtualinterruptflag(VIF)&virtualinterruptpendingUsedinmultitaskingenvironmentControlRegistersThePentiumemploys432-bitcontrolregisterstocontrolvariousaspectofprocessoroperationsMMXRegistersPentiumIImakesitselfhave864-bitMMXregistersbyusingaliastechniques80-bitfloatingpointregistersareusedtostoreMMXdataSpecifically,low-order64bitsareusedtoform8MMXregistersMappingofMMXregisterstoFPRegistersCharacteristicsofMMXRegisterDirectlyaccessOnceaMMXinstructionisexecuted,theFPtagwordismarkedinvalidTheEMMS(emptyMMXstate)instructioncanresettheFPtagwordtoindicatethatallregistersareemptyUsingEMMSinstructionattheendofMMXcodeblocksothatsubsequentFPinstructionscanuseFPregistersproperlyWhenavalueiswrittentoaMMXregister,64~79bitsaresettoall1InterruptProcessing–

InterruptsandexceptionsInterruptsandexceptionsInterruptsandexceptionscancauseCPUsuspendSavecontextandexecutetheserviceroutineInterruptisgeneratedbyhardwareandexceptionfromsoftwareSourcesofInterruptsandexceptionsMaskableinterrupts:IF=1,receivesignalfromINTNonmaskable

interrupts:receivesignalfromNMICPU-detectedexceptions:CPUencounteranerrorProgrammedexceptions:aprogramerroroccursInterruptProcessing–

InterruptVectorTableInterruptvectortablecontains25632-bitinterruptvectorEverytypeofinterruptisassignedanumber,usedtoindextheinterruptvectortableAninterruptvectoristheaddressofinterruptserviceroutineforthatinterruptnumberSeetable12.2,where,32~255areuserinterruptvectorsPriorityindescendingorderDebugexceptions,externalinterrupts,fetcherror,decodingerror,executingerrorInterruptProcessing–

InterrupthandlingCurrentstacksegmentregisterandextendedstackpointerregisterarepushedontostackPushthevalueofEFLAGSregisterClear(disable)interruptandtrapflagsPushcurrentcodesegmentpointerandinstructionpointerPusherrorcode,ifitexi