周期实验报告单CPU设计含I O

// wirei_or=r_type&func[5]&~func[4]&~func[3]&func[2]&~func[1]& // wirei_xor=r_type&func[5]&~func[4]&~func[3]&func[2]&func[1]& // wirei_sll=r_type&~func[5]&~func[4]&~func[3]&~func[2]&~func[1] wirei_srl=r_type&~func[5]&~func[4]&~func[3]&~func[2]&func[1]& // wirei_sra=r_type&~func[5]&~func[4]&~func[3]&~func[2]&func[1] // wirei_jr=r_type&~func[5]&~func[4]&func[3]&~func[2]&~func[1] //I_type,op // wirei_addi=~op[5]&~op[4]&op[3]&~op[2]&~op[1]& // wirei_andi=~op[5]&~op[4]&op[3]&op[2]&~op[1]& // wirei_ori=~op[5]&~op[4]&op[3]&op[2]&~op[1]& // wirei_xori=~op[5]&~op[4]&op[3]&op[2]&op[1]& // wire =op[5]&~op[4]&~op[3]&~op[2]&op[1]& // wire =op[5]&~op[4]&op[3]&~op[2]&op[1]& // wirei_beq=~op[5]&~op[4]&~op[3]&op[2]&~op[1]& // wirei_bne=~op[5]&~op[4]&~op[3]&op[2]&~op[1]& // wirei_lui=~op[5]&~op[4]&op[3]&op[2]&op[1]& //J-type,op // wire =~op[5]&~op[4]&~op[3]&~op[2]&op[1]& // wirei_jal=~op[5]&~op[4]&~op[3]&~op[2]&op[1]& assignpcsource[1]=i_jr|i_j| assignpcsource[0]=(i_beq&z)|(i_bne&~z)|i_j|i_jal assignwreg=i_add|i_sub|i_and| |i_xor i_sll|i_srl|i_sra|i_addi|i_andi i_ori|i_xori|i_lw|i_lui| assignaluc[3]= assignaluc[2]=i_sub|i_or|i_srl|i_sra|i_ori|i_lui|i_beq|; assignaluc[1]=i_xor|i_sll|i_srl|i_sra|i_xori| assignaluc[0]=i_and|i_andi|i_or|i_sll|i_srl|i_sra| assign =i_sll|i_srl|i_sra assignaluimm=i_addi|i_andi|i_ori|i_xori|i_lw|i_lui| =i_addi|i_lw|i_sw|i_beq| assign = assign = assign =i_addi|i_andi|i_ori|i_xori|i_lw| assign = 4'bx000:s=a+ //x000 4'bx100:s=a- //x100 4'bx001:s=a& //x001 4'bx101:s=a| //x101 4'bx010:s=a^ //x010 4'bx110:s= //x110LUI:imm<< 4'b0011:s= //0011SLL:rd<-(rt<< 4'b0111:s= //0111SRL:rd<-(rt>>sa)) 4'b1111:s=$signed(b)>>> //1111SRA:rd<-(rt>>sa) default:s= mem_clkclkmem_clkclk1.1.moduleoutputalways@(posedge clock5=regclock5=input 进sc_instmem.mifsc_datamem.mifdatamem和进利用不同的地址来区分是DataRAM还是I/O。1.1.assignwrite_datamem_enablewrite_enable&~addr[7//5.//modulemux2x327.//thatis,theaddressspaceofdatamemisfrom000000to011111word(49.lpm_ram_dq_dramrt3,10.io_output_regio_output_regx26.//whenaddress[7]=0,meanstheaccessistothe4.mux2x322.assignwrite_io_output_reg_enablewrite_enable&addr[7//2.input[31:0]3.input2.input[31:0]3.input4.input5.//resetsignal.ifnecessary,canusethissignaltoresettheoutputto7.output[31:0]8.reg[31:0]out_port0;//output9.reg[31:0]out_port1;//output10.reg[31:0]11.reg[31:0]13.always@(posedgeio_clkornegedge if(clrn== begin// out_port0 out_port1<=0;//resetalltheoutputportto if(write_io_enable== case 6'b100000:out_port0<=datain;// 6'b100001:out_port1<=datain;// 6'b100010:out_port2<= 6'b100011:out_port3<= //moreports，可根据需要设计的输出端口 1.1.modulesc_input4(sw0,sw1,sw2,sw3,3.inputsw0,sw1,sw2,5.wire[31:0]in_port={28'b0,sw3,sw2,sw1,7.4.output[31:0]1.1.modulesc_output(out_port,hex0,3.output[6:0]hex0,5.wire[3:0]data1=out_port%9.sevenseghex11(data2,13.input[3:0]15.reg[6:0]16.always@14.output12.modulesevenseg(data,8.sevenseghex00(data1,6.wire[3:0]data2=out_port/2.input[31:0]18.gfe_dcba7LED19.654_3210DE1-SOC20.0ledsegments7'b100_0000DE1-SOC21.1:ledsegments=22.2:ledsegments=23.3:ledsegments=24.4:ledsegments=25.5:ledsegments=26.6:ledsegments=27.7:ledsegments=28.8:ledsegments=29.9:ledsegments=30.defaultledsegments7'b111_