DDS信号发生器电路设计方案

。直接数字合成(DirectDigitalSynthesis、DDS)是一种新的频率合成技术和信号产生的方法。直接数字频率合成器(DDS)具有超高速的频率转突出优点。因此这种份。系统时钟为f输出频率为f。根据公式f=f可知，只要选择恰当的clkoutoutclk频率控制字，就可以得到所需要的输出频率f。outROM找表，其部存储一个完整的正弦波的数字幅度样便实现了从数5、低通滤波器(LPF)DA的波形是梯形状的，将它通过低通滤波器后就可以看到平00p预分频模块由32位加法器和32位锁存器构成。根据公式f=f可知，outclkN为32，f=50MHz，要使f=220Hz，只需求出M的值，然后对其进行累加。clkout根据公式f=f可知，要使输出频率可控，则DDS累加器的位数要与outclkout控制模块块模块因为如果包含低位，则一个周期中将会出现的多于28(256)个值，就不能、*CS：片选信号输入线(选通数据锁存器)，低电平有效；*WR1：数据锁存器写选通输入线，负脉冲(脉宽应大于500ns)有*XFER：数据传输控制信号输入线，低电平有效，负脉冲(脉宽应1&5、偏置平衡(调零端)1&8、偏置平衡(调零端)使输入端(即2号脚)开路，用万用表对OP07芯片输出进行调零，由反向⑦低通滤波器(LPF)使输入端(即3号脚)开路，用万用表对OP07芯片进行调零。二阶低通件(VectorWaveformFile)，然后将要进行仿真的节点(Nodes)添加到仿真文件中，保存后打开仿真工具 (SimulatorTool)，选择功能仿真(Functional)，生成网表(Generate告文件(Report)。通过公式f=f求出的M的值为“1000”来一个时钟outclk由于f=M，又因为输出频率围为50Hz~10kHz，所以进位高位的进位较out3、使用了示波器部增益()；。位器，便于对低通滤。转IBRARYIEEEUSEIEEESTDLOGIC1164.ALL;USEIEEESTDLOGICARITH.ALL;USEIEEESTDLOGICUNSIGNED.ALL;ENTITYzhishuISPORTMOUTSTD_LOGIC_VECTOR(31DOWNTO0));NTITYARCHITECTUREfuncOFzhishuISINM<="1000";CHITECTUREIBRARYIEEEUSEIEEESTDLOGIC1164.ALL;USEIEEESTDLOGICARITH.ALL;USEIEEESTDLOGICUNSIGNED.ALL;ENTITYbcxuanzeISPORTbcxzmaichongINSTDLOGICbcBUFFERSTDLOGIC_VECTOR(19DOWNTO0));NTITYARCHITECTUREfuncOFbcxuanzeISSIGNALbcSTDLOGIC_VECTOR(19DOWNTO0):="001";SIGNALbcSTDLOGIC_VECTOR(19DOWNTO0):="010";SIGNALbcSTDLOGIC_VECTOR(19DOWNTO0):="010";SIGNALbcSTDLOGIC_VECTOR(19DOWNTO0):="100";SIGNALbcSTDLOGIC_VECTOR(19DOWNTO0):="000";SIGNALtmpSTDLOGICVECTOR9DOWNTO0);INESSbcxzmaichongINngEVENTANDbcxzmaichongTHENbcbc;bcbc2;bcbc3;bcbc4;bcbc5;bcbc;ENDIF;ROCESSCHITECTUREIBRARYIEEEUSEIEEESTDLOGIC1164.ALL;USEIEEESTDLOGICARITH.ALL;USEIEEESTDLOGICUNSIGNED.ALL;ENTITYkongzhiISPORTkeyINSTDLOGICICM:INSTD_LOGIC_VECTOR(19DOWNTO0);foutBUFFERSTDLOGICVECTORDOWNTO));NTITYARCHITECTUREfuncOFkongzhiISINCESSkeyclrINDkeyTHENutMENDIF;ENDIF;fout";ENDIF;ROCESSCHITECTUREIBRARYIEEEUSEIEEESTDLOGIC1164.ALL;USEIEEESTDLOGICARITH.ALL;USEIEEESTDLOGICUNSIGNED.ALL;ENTITYxianshiISPORTfoutin:INSTD_LOGIC_VECTOR(19DOWNTO0);ICnumOUTSTDLOGIC_VECTOR(6DOWNTO0);numOUTSTDLOGIC_VECTOR(6DOWNTO0);numOUTSTDLOGIC_VECTOR(6DOWNTO0);numOUTSTDLOGIC_VECTOR(6DOWNTO0);numOUTSTDLOGICVECTOR(6DOWNTO0));NTITYARCHITECTUREfuncOFxianshiISecINTEGERINVINTEGERfoutinCESSclkINDclkTHENCASEdecREM10ISWHEN0=>num1<="1000000";WHEN1=>num1<="1111001";WHEN2=>num1<="0100100";HENnum0110000";HENnum1<="0011001";HENnum0010010";HENnum="0000010";HENnum111000";HENnum<="0000000";HENnum<="0010000";HENOTHERS=>num1<="1111111";CASECASE(decREM100)/10ISHENnum="1000000";HENHENnum"0100100";HENnum0110000";HENnum2<="0011001";HENnum0010010";HENnum="0000010";HENnum111000";HENnum<="0000000";HENnum<="0010000";HENOTHERSnum<="1111111";CASECASE(decREM1000)/100ISHENnum="1000000";WHEN1=>num3<="1111001";HENnum"0100100";HENnum0110000";HENnum3<="0011001";HENnum0010010";HENnum="0000010";HENnum111000";HENnum<="0000000";HENnum<="0010000";HENOTHERS=>num1<="1111111";CASECASE(decREM10000)/1000ISHENnum="1000000";HENHENnum"0100100";HENnum0110000";HENnum4<="0011001";HENnum0010010";HENnum="0000010";HENnum111000";HENnum<="0000000";HENnum<="0010000";HENOTHERS=>num1<="1111111";ENDCASE;CASEdec/10000ISWHEN0=>num5<="1000000";HENHENHENHENHENHENHENHENHENHENSEENDIF;num"0100100";num0110000";num5<="0011001";num0010010";num="0000010";num111000";num<="0000000";num<="0010000";OTHERSnum<="1111111";ROCESSCHITECTUREIBRARYIEEEUSEIEEESTDLOGIC1164.ALL;USEIEEESTDLOGICARITH.ALL;USEIEEESTDLOGICUNSIGNED.ALL;ENTITYzhuanhuanISPORTzh_in:INSTD_LOGIC_VECTOR(19DOWNTO0);ENTITYfangboIShoutOUTSTDLOGICVECTORDOWNTONTITYARCHITECTUREfuncOFzhuanhuanISINPROCESS(zh_in)INzhoutzhinzhoutzhinzhoutzhinzhoutzhinzhoutzhinzhoutzhinzhoutzhinzhoutzhinROCESSCHITECTUREIBRARYIEEEUSEIEEESTDLOGIC1164.ALL;USEIEEESTDLOGICARITH.ALL;USEIEEESTDLOGICUNSIGNED.ALL;PORTfbinSTDLOGICLOGICfboutOUTSTDLOGICVECTORDOWNTO));NTITYARCHITECTUREfuncOFfangboISINPROCESSfbinfbclk)INANDfbclkTHENFORiINTO7LOOPfbouti=fb_in;LOOPENDIF;ROCESSCHITECTUREIBRARYIEEEUSEIEEESTDLOGIC1164.ALL;USEIEEESTDLOGICARITH.ALL;USEIEEESTDLOGICUNSIGNED.ALL;ENTITYxuanzeISPORT(xzmaichong:INSTD_LOGIC;OGICVECTORDOWNTOOGICVECTORDOWNTOOGICVECTORDOWNTOOGICVECTORDOWNTOoutputOUTSTDLOGICVECTORDO