基于VHDL电子日历的设计

1历摘要2绪论 3 3计 4 4 5 6 6 7 8 8 9 3第一章绪论设计4日历显示格式5报告要求6章设计原理图图电子日历实验原理图78设计结果与仿真LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT60ISPORT(CLK:INSTD_LOGIC;Q1,Q2:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUT:OUTSTD_LOGIC);ENDCNT60;ARCHITECTUREONEOFCNT60ISSIGNALQ11,Q22:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK)BEGINIFCLK'EVENTANDCLK='1'THENQ11<=Q11+1;IFQ11=9THENQ11<=(OTHERS=>'0');Q22<=Q22+1;ENDIF;IFQ22=5ANDQ11=9THENQ22<="0000";Q11<="0000";COUT<='1';ELSECOUT<='0';ENDIF;ENDIF;ENDPROCESS;Q1<=Q11;Q2<=Q22;9图图进制计数器仿真图LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT24ISPORT(CLK:INSTD_LOGIC;Q1,Q2:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUT:OUTSTD_LOGIC);ENDCNT24;ARCHITECTUREONEOFCNT24ISSIGNALQ11,Q22:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK)BEGINIFCLK'EVENTANDCLK='1'THENQ11<=Q11+1;IFQ11=9THENQ11<=(OTHERS=>'0');ENDIF;QQ11<="0000";COUT<='1';SECOUTENDIF;ENDIF;ESSQQQQ;图图进制计数器仿真图LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYWEEKISPORT(CLK:INSTD_LOGIC;W:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUT:OUTSTD_LOGIC);ENDWEEK;ARCHITECTUREONEOFWEEKISSIGNALQ11:STD_LOGIC_VECTOR(3DOWNTO0);图进制计数器仿真图LIBRARYIEEEUSEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYDAYISPORTCLK:INSTD_LOGIC;CQ1:OUTSTD_LOGIC_VECTOR(3DOWNTO0);CQ2:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUTOUTSTDLOGIC;ARCHITECTUREONEOFDAYISSIGNALCQCQSTDLOGICVECTORDOWNTO0);SCLKENDIF;CQCQ<="0001";COUT<='1';SECOUTENDIF;ENDIFESS图进制计数器仿真图RARYIEEEUSEIEEESTDLOGIC64.ALL;USEIEEESTDLOGICUNSIGNEDALLENTITYMONTHISportclkINSTD_LOGIC;GICcqOUTSTDLOGICVECTORDOWNTOEND;ARCHITECTUREbehavOFMONTHIScqSTDLOGICVECTORDOWNTOSclkIFcqTHENcqcqcq";ENDIF;IFcqandcqTHENcqcqcout='1';ELSEcout<='0';ENDIF;ENDIF;ESS月模块仿真图LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYYEARISPORT(CLK:INSTD_LOGIC;Y1,Y2:OUTSTD_LOGIC_VECTOR(3DOWNTO0););ENDYEAR;ARCHITECTUREONEOFYEARISSIGNALQ1,Q2:STD_LOGIC_VECTOR(3DOWNTO0);EGINPROCESS(CLK)EGINIFCLK'EVENTANDCLK='1'THENQ1<=Q1+1;IFQ1=9THENQ1<=(OTHERS=>'0');Q2<=Q2+1;ENDIF;IFQANDQ1=9THENQ2<="0000";Q1<="0000";COUT<='1';ELSECOUT<='0';ENDIF;ENDIF;ENDPROCESS;Y1<=Q1;Y2<=Q2;图年低两位模块仿真图LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYYEARISPORT(CLK:INSTD_LOGIC;Y3,Y4:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUT:OUTSTD_LOGIC);ENDYEAR;ARCHITECTUREONEOFYEARISSIGNALQ11,Q22:STD_LOGIC_VECTOR(3DOWNTO0);EGINPROCESS(CLK)EGINIFCLK'EVENTANDCLK='1'THENQ11<=Q11+1;IFQ11=9THENQ11<=(OTHERS=>'0');Q22<=Q22+1;ENDIF;IFQANDQ11=9THENQ22<="0000";Q11<="0000";COUT<='1';ELSECOUT<='0';ENDIF;ENDIF;ENDPROCESS;Y3<=Q11;Y4<=Q22;图高两位年模块仿真图LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYJIAODUIISPORT(K1,K2:INSTD_LOGIC;WI,DI,MI,YLI,YHI:INSTD_LOGIC;WO,DO,MO,YLO,YHO:OUTSTD_LOGIC);ENDJIAODUI;ARCHITECTUREBEHAVOFJIAODUIISSIGNALA:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(K1,K2)BEGINIFK1'EVENTANDK1='1'THENA<=A+1;A<="0000";ENDIF;ENDIF;CASEAISWHEN000"=>WO<=WI;DO<=DI;MO<=MI;YLO<=YLI;YHO<=YHI;WHEN"0001"=>WO<=K2;DO<='0';MO<='0';YLO<='0';YHO<='0';WHEN"0010"=>WO<='0';DO<=K2;MO<='0';YLO<='0';YHO<='0';WHEN"0011"=>WO<='0';DO<='0';MO<=K2;YLO<='0';YHO<='0';WHEN"0100"=>WO<='0';DO<='0';MO<='0';YLO<=K2;YHO<='0';WHEN"0101"=>WO<='0';DO<='0';MO<='0';YLO<='0';YHO<=K2;WHENOTHERS=>NULL;CASEROCESS图按下六次恢复正常LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCONTROLISPORT(WL,WH,DL,DH,ML,MH,YL,YH,Y1L,Y1H:INSTD_LOGIC_VECTOR(3DOWNTO0);Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCONTROL;ARCHITECTUREONEOFCONTROLISEGINQ10<=Y1H;Q9<=Y1L;Q8<=YH;Q7<=YL;Q6<=MH;Q5<=ML;Q4<=DH;Q3<=DL;Q2<=W