外文翻译直接数字频率合成器

AllAboutDirectDigitalByEvaMurphy ColmSlattery WhatisDirectDigitalDirectdigitalsynthesis(DDS)isamethodofproducinganogwaveform—usuallyasinewave—bygeneratingatime-varyingsignalindigitalformandthenperformingadigital-to-ogconversion.BecauseoperationswithinaDDSdeviceareprimarilydigital,itcanofferfastswitchingbetweenoutputfrequencies,finefrequencyresolution,andoperationoverabroadspectrumoffrequencies.Withadvancesindesignandprocesstechnology,today’sDDSdevicesareverycompactanddrawlittlepower.Whywouldoneuseadirectdigitalsynthesizer(DDS)?Aren’tthereothermethodsforeasilygeneratingfrequencies?Theabilitytoaccurayproduceandcontrolwaveformsofvariousfrequenciesandprofileshas eakeyrequirementcommontoanumberofindustries.Whetherprovidingagilesourcesoflow-phase-noisevariable-frequencieswithgoodspuriousperformanceforcommunications,orsimplygeneratingafrequencystimulusinindustrialorbiomedicaltestequipmentapplications,convenience,compactness,andlowcostareimportantdesignconsiderations.Manypossibilitiesforfrequencygenerationareopentoadesigner,rangingfromphase-locked-loop(PLL)-basedtechniquesforveryhigh-frequencysynthesis,todynamicprogrammingofdigital-to-ogconverter(DAC)outputstogeneratearbitrarywaveformsatlowerfrequencies.ButtheDDStechniqueisrapidlygainingacceptanceforsolvingfrequency-(orwaveform)generationrequirementsinbothcommunicationsandindustrialapplicationsbecausesingle-chipICdevicescangenerateprogrbleogoutputwaveformssimplyandwithhighresolutionandaccuracy.Furthermore,thecontinualimprovementsinbothprocesstechnologyanddesignhaveresultedincostandpowerconsumptionlevelsthatwerepreviouslyunthinkablylow.Forexample,theAD9833,aDDS-based

Figure1.TheAD9833-aone-chipwaveformwaveformgenerator(Figure1),operatingat5.5Vwitha25-MHzclock,consumesumpowerof30WhatarethemainbenefitsofusingaDDSdevicesliketheAD9833areprogrammedthroughahighspeedserialperipheral-interface(SPI),andneedonlyanexternalclocktogeneratesimplesinewaves.DDSdevicesarenowavailablethatcangeneratefrequenciesfromlessthan1Hzupto400MHz(basedona1-GHzclock).Thebenefitsoftheirlowpower,lowcost,andsinglesmallpackage,combinedwiththeirinherentexcellentperformanceandtheabilitytodigitallyprogram(andre-program)theoutputwaveform,makeDDSdevicesanextremelyattractivesolution—preferabletoless-flexiblesolutionscomprisingaggregationsofdiscreteelements.WhatkindofoutputscanIgeneratewithatypicalDDSDDSdevicesarenotlimitedtopurelysinusoidaloutputs.Figure2showsthesquare-,triangular-,andsinusoidaloutputsavailablefromanAD9833.HowdoesaDDSdevicecreateasineHere’sabreakdownoftheinternalcircuitryofaDDSdevice:itsmaincomponentsareaphaseaccumulator,ameansofphase-to-amplitudeconversion(oftenasinelook-uptable),andaTheseblocksarerepresentedinFigureADDSproducesasinewaveata

Figure2.Square-,triangular-,andsinusoidaloutputsfromaDDS.frequency.Thefrequencydependsontwovariables,thereference-clockfrequencyandthebinarynumberprogrammedintothefrequencyregister(tuningword).Thebinarynumberinthefrequencyregisterprovidesthemaininputtothephaseaccumulator.Ifasinelook-uptableisused,phaseaccumulator

Figure3.Componentsofadirectdigitalaphase(angle)addressforthelook-uptable,whichoutputsthedigitalvalueofamplitude—correspondingtothesineofthatphaseangle—totheDAC.TheDAC,inturn,convertsthatnumbertoacorrespondingvalueofogvoltageorcurrent.Togenerateafixed-frequencysinewave,aconstantvalue(thephaseincrement—whichisdeterminedbythebinarynumber)isaddedtothephaseaccumulatorwitheachclockcycle.Ifthephaseincrementislarge,thephaseaccumulatorwillstepquicklythroughthesinelook-uptableandthusgenerateahighfrequencysinewave.Ifthephaseincrementissmall,thephaseaccumulatorwilltakemanymoresteps,accordinglygeneratingaslowerwaveform.WhatdoyoumeanbyacompleteTheintegrationofaD/AconverterandaDDSontoasinglechipiscommonlyknownasacompleteDDSsolution,apropertycommontoallDDSdevicesfromLet’stalksomemoreaboutthephaseaccumulator.HowdoesitContinuous-timesinusoidalsignalshavearepetitiveangularphaserangeof02.Thedigitalimplementationisnodifferent.Thecounter’scarryfunctionallowsthephaseaccumulatortoactasaphasewheelintheDDSimplementation.Tounderstandthisbasicfunction,visualizethesine-waveoscillationasavectorrotatingaroundaphasecircle(seeFigure4).Eachdesignatedpointonthephasewheelcorrespondstotheequivalentpointonacycleofasinewave.Asthevectorrotatesaroundthewheel,visualizethatthesineoftheanglegeneratesacorrespondingoutputsinewave.Onerevolutionofthevectoraroundthephasewheel,ataconstantspeed,resultsinonecompletecycleoftheoutputsinewave.Thephaseaccumulatorprovidestheequallyspacedangular panyingthelinearrotationaroundthephasewheel.Thecontentsofthephaseaccumulatorcorrespondtothepointsonthecycleoftheoutputsinewave.Figure4.DigitalphaseThephaseaccumulatorisactuallyamodulo-Mcounterthatincrementsitsstorednumbereachtimeitreceivesaclockpulse.Themagnitudeoftheincrementisdeterminedbythebinary-codedinputword(M).Thiswordformsthephasestepbetweenreference-clockupdates;iteffectivelysetshowmanypointstoskiparoundthephasewheel.Thelargerthejumpsize,thefasterthephaseaccumulatoroverflowsandcompletesitsequivalentofasine-wavecycle.Thenumberofdiscretephasepointscontainedinthewheelisdeterminedbytheresolutionofthephaseaccumulator(n),whichdeterminesthetuningresolutionoftheDDS.Forann=28-bitphaseaccumulator,anMvalueof0000...0001wouldresultinthephaseaccumulatoroverflowingafter28reference-clockcycles(increments).IftheMvalueischangedto0111...1111,thephaseaccumulatorwilloverflowafteronly2reference-clockcycles(theminimumrequiredbyNyquist).ThisrelationshipisinthebasictuningequationforDDS

MfOUT=outputfrequencyoftheDDSM=binarytuningwordfC=internalreferenceclockfrequency(systemclock)n=lengthofthephaseaccumulator,inbitsChangestothevalueofMresultinimmediateandphase-continuouschangesintheoutputfrequency.Noloopsettlingtimeisincurredasinthecaseofaphase-lockedAstheoutputfrequencyisincreased,thenumberofsamplespercycledecreases.Sincesamplingtheorydictatesthatatleasttwosamplespercyclearerequiredtoreconstructtheoutputwaveform,theumfundamentaloutputfrequencyofaDDSisfC/2.However,forpracticalapplications,theoutputfrequencyislimitedtosomewhatlessthanthat,improvingthequalityofthereconstructedwaveformandpermittingfilteringontheoutput.Whengeneratingaconstantfrequency,theoutputofthephaseaccumulatorincreaseslinearly,sotheogwaveformitgeneratesisinherentlyaramp.ThenhowisthatlinearoutputtranslatedintoasineAphase-to-amplitudelookuptableisusedtoconvertthephase-accumulator’sinstantaneousoutputvalue(28bitsforAD9833)—withunneededless-significantbitseliminatedbytruncation—intothesine-waveamplitudeinformationthatispresentedtothe(10-bit)D/Aconverter.TheDDSarchitectureexploitsthesymmetricalnatureofasinewaveandutilizesmaplogictosynthesizeacompletesinewavefromone-quarter-cycleofdatafromthephaseaccumulator.Thephase-to-amplitudelookup

Figure5.SignalflowthroughtheDDStablegeneratestheremainingdatabyreadingforwardthenbackthroughthelookuptable.ThisisshownpictoriallyinFigure5.WhatarepopularusesforApplicationscurrentlyusingDDS-basedwaveformgenerationfallintotwoprincipalcategories:Designersofcommunicationssystemsrequiringagile(i.e.,immediayresponding)frequencysourceswithexcellentphasenoiseandspuriousperformanceoftenchooseDDSforitscombinationofspectralperformanceandfrequency-tuningresolution.SuchapplicationsincludeusingaDDSformodulation,asareferenceforaPLLtoenhanceoverallfrequencytunability,asalocaloscillator(LO),orevenfordirectRFtransmission.Alternatively,manyindustrialandbiomedicalapplicationsuseaDDSasaprogrblewaveformgenerator.BecauseaDDSisdigitallyprogrble,thephaseandfrequencyofawaveformcanbeeasilyadjustedwithouttheneedtochangetheexternalcomponentsthatwouldnormallyneedtobechangedwhenusingtraditionalog-programmedwaveformgenerators.DDSpermitssimpleadjustmentsoffrequencyinrealtimetolocateresonantfrequenciesorcompensatefortemperaturedrift.SuchapplicationsincludeusingaDDSinadjustablefrequencysourcestomeasureimpedance(forexampleinanimpedance-basedsensor),togeneratepulse-wavemodulatedsignalsformicro-actuation,ortoexamineattenuationinLANsorephonecables.WhatdoyouconsidertobethekeyadvantagesofDDStodesignersofreal-worldequipmentandsystems?Today’scost-competitive,high-performance,functionallyintegratedDDSICs ingcommoninbothcommunicationsystemsandsensorapplications.Theadvantagesthatmakethemattractivetodesignengineersinclude:digitallycontrolledmicro-hertzfrequency-tuningandsub-degreephase-tuningextremelyfasthopspeedintuningoutputfrequency(orphase);phase-continuousfrequencyhopswithnoovershoot/undershootorog-relatedloopsettling-timeanomalies,thedigitalarchitectureofDDSeliminatestheneedforthemanualtuningandtweakingrelatedtocomponentagingandtemperaturedriftinogsynthesizersolutions,andthedigitalcontrolinterfaceoftheDDSarchitecturefacilitatesanenvironmentwheresystemscanberemoycontrolledandoptimizedwithhighresolutionunderprocessorHowwouldIuseaDDSdeviceforFSKBinaryfrequency-shiftkeying(usuallyreferredtosimplyasFSK)isoneofthesimplestformsofdataencoding.Thedataistransmittedbyshiftingthefrequencyofacontinuouscarriertooneoftwodiscretefrequencies(hencebinary).Onefrequency,f1,(perhapsthehigher)isdesignatedasthemarkfrequency(binaryone)andtheother,f0,asthespacefrequency(binaryzero).Figure6showsanexampleoftherelationshipbetweenthemark-spacedataandthetransmittedsignal.ThisencodingschemeiseasilyimplementedusingaDDS.TheDDSfrequencytuningword,representingtheoutputfrequencies,issettotheappropriatevaluestogeneratef0andf1astheyoccurinthepatternof0sandtobetransmitted.Theuserthetworequiredtuningwordsinto

Figure6.FSKdevicebeforetransmission.InthecaseoftheAD9834,twofrequencyregistersareavailabletofacilitateconvenientFSKencoding.Adedicatedpinonthedevice(FSELECT)acceptsthemodulatingsignalandselectstheappropriatetuningword(orfrequencyregister).TheblockdiagraminFigure7demonstratesasimpleimplementationofFSKencoding.AndhowaboutPSKPhase-shiftkeying(PSK)isanothersimpleformofdataencoding.InPSK,thefrequencyofthecarrierremainsandthephaseofthetransmittedsignalisvariedtoconveytheinformation.

Figure7.ADDS-basedFSKOftheschemesto plishPSK,thesimplest-knownasbinaryPSK(BPSK)—usesjusttwosignalphases,0degreesand180degrees.BPSKencodes0phaseshiftforalogic1inputand180phaseshiftforalogic0input.Thestateofeachbitisdeterminedaccordingtothestateoftheprecedingbit.Ifthephaseofthewavedoesnotchange,thesignalstatestaysthesame(loworhigh).Ifthephaseofthewavereverses(changesby180degrees),thenthesignalstatechanges(fromlowtohigh,orfromhightolow).PSKencodingiseasilyimplementedwithDDSICs.Mostofthedeviceshaveaseparateinputregister(aphaseregister)thatcanbeloadedwithaphasevalue.Thisvalueisdirectlyaddedtothephaseofthecarrierwithoutchangingitsfrequency.Changingthecontentsofthisregistermodulatesthephaseofthecarrier,thusgeneratingaPSKoutputsignal.Forapplicationsthatrequirehighspeedmodulation,theAD9834allowsthepreloadedphaseregisterstobeselectedusingadedicatedtogglinginputpin(PSELECT),whichalternatesbetweentheregistersandmodulatesthecarrierasrequired.MoresophisticatedformsofPSKemployfour-oreight-wavephases.ThisallowsbinarydatatobetransmittedatafasterrateperphasechangethanispossiblewithBPSKmodulation.Infour-phasemodulation(quadraturePSKorQPSK),thepossiblephaseanglesare0,+90,–90,and180degrees;eachphaseshiftcanrepresenttwosignalelements.TheAD9830,AD9831,AD9832,andAD9835providefourphaseregisterstoallowcomplexphasemodulationschemestobeimplementedbycontinuouslyupdatingdifferentphaseoffsetstotheregisters.CanmultipleDDSdevicesbesynchronizedfor,say,I-QItispossibletousetwosingleDDSdevicesthatoperateonthesamemasterclocktooutputtwosignalswhosephaserelationshipcanthenbedirectlycontrolled.InFigure8,twoAD9834sareprogrammedusingonereferenceclock,withthesameresetpinbeingusedtoupdatebothparts.Usingthissetup,itispossibletodoI-QFigure8.MultipleDDSICsinFigure8.MultipleDDSICsinsynchronousmode.Aresetmustbeassertedafterpower-upandpriortotransferringanydatatotheDDS.ThissetstheDDSoutputtoaknownphase,whichservesasthecommonreferencepointthatallowssynchronizationofmultipleDDSdevices.WhennewdataissentsimultaneouslytomultipleDDSunits,acoherentphaserelationshipcanbemaintained,andtheirrelativephaseoffsetcanbepredictablyshiftedbymeansofthephase-offsetregister.TheAD9833andAD9834have12bitsofphaseresolution,withaneffectiveresolutionof0.1degree.[ForfurtherdetailsonsynchronizingmultipleDDSunitspleaseseeApplicationNoteAN-605.]WhatarethekeyperformancespecsofaDDSbasedPhasenoise,jitter,andspurious-dynamicrangePhasenoiseisameasure(dBc/Hz)oftheshort-termfrequencyinstabilityoftheoscillator.Itismeasuredasthesingle-sidebandnoiseresultingfromchangesinfrequency(indecibelsbelowtheamplitudeattheoperatingfrequencyoftheoscillatorusinga1-Hzbandwidth)attwoormorefrequencydiscementsfromtheoperatingfrequencyoftheoscillator.Thismeasurementhasparticularapplicationtoperformanceintheogcommunicationsindustry.DoDDSdeviceshavegoodphaseNoiseinasampledsystemdependsonmanyfactors.Reference-clockjittercanbeseenasphasenoiseonthefundamentalsignalinaDDSsystem;andphasetruncationmayintroduceanerrorlevelintothesystem,dependingonthecodewordchosen.Foraratiothatcanbeexactlyexpressedbyatruncatedbinary-codedword,thereisnotruncationerror.Forratiosrequiringmorebitsthanareavailable,thefortheAD9834.Outputfrequencyis2MHzandMclockis50MHz.resultingphasenoisetruncationerrorresultsinspursinaspectralplot.Theirmagnitudesanddistributiondependsonthecodewordchosen.TheDACalsocontributestonoiseinthesystem.DACzationorlinearityerrorswillresultinbothnoiseandharmonics.Figure9showsaphasenoiseplotforatypicalDDSdevice—inthiscaseanAD9834.WhataboutJitteristhedynamicdiscementofdigitalsignaledgesfromtheirlong-termaveragepositions,measuredindegreesrms.Aperfectoscillatorwouldhaverisingandfallingedgesoccurringatpreciselyregularmomentsintimeandwouldnevervary.This,ofcourse,isimpossible,aseventhebestoscillatorsareconstructedfromrealcomponentswithsourcesofnoiseandotherimperfections.Ahigh-quality,low-phase-noisecrystaloscillatorwillhavejitteroflessthan35picoseconds(ps)ofperiodjitter,accumulatedovermanymillionsofclockedgesJitterinoscillatorsiscausedbythermalnoise,instabilitiesintheoscillatorelectronics,externalinterferencethroughthepowerrails,ground,andeventheoutputconnections.Otherinfluencesincludeexternalmagneticorelectricfields,suchasRFinterferencefromnearbytransmitters,whichcancontributejitteraffectingtheoscillator’soutput.Evenasimpleamplifier,inverter,orbufferwillcontributejittertoasignal.ThustheoutputofaDDSdevicewilladdacertainamountofjitter.Sinceeveryclockwillalreadyhaveanintrinsiclevelofjitter,choosinganoscillatorwithjitteriscriticaltobeginwith.Dividingdownthefrequencyofahigh-frequencyclockisonewaytoreducejitter.Withfrequencydivision,thesameamountofjitteroccurswithinalongerperiod,reducingitspercentageofsystemtime.Ingeneral,toreduceessentialsourcesofjitterandavoidintroducingadditionalsources,oneshoulduseastablereferenceclock,avoidusingsignalsandcircuitsthatslewslowly,andusethehighestfeasiblereferencefrequencytoallowincreasedSpurious-DynamicRange(SFDR)referstotheratio(measuredindecibels)betweenthehighestlevelofthefundamentalsignalandthehighestlevelofanyspurious,signal—includingaliasesandharmonicallyrelatedfrequencycomponents—inthespectrum.FortheverybestSFDR,itisessentialtobeginwithahigh-qualityoscillator.SFDRisanimportantspecificationinanapplicationwherethefrequencyspectrumisbeingsharedwithothercommunicationchannelsandapplications.Ifatransmitter’soutputsendsspurioussignalsintootherfrequencybands,theycancorrupt,orinterruptneighboringsignals.TypicaloutputplotstakenfromanAD9834(10-bitDDS)witha50MHzmasterclockareshowninFigure10.In(a),theoutputfrequencyisexactly1/3ofthemasterclockfrequency(MCLK).Becauseofthejudiciouschoiceoffrequencies,therearenoharmonicfrequenciesinthe25-MHzwindow,aliasesareminimized,andthespuriousbehaviorappearsexcellent,withallspursatleast80dBbelowthesignal(SFDR=80dB).Thelowerfrequencysettingin(b)hasmorepointstoshapethewaveform(butnotenoughforareallycleanwaveform),andgivesamorerealisticpicture;thelargestspur,atthesecond-harmonicfrequency,isabout50dBbelowthesignal(SFDR=50dB).(a)fOUT= (b)fOUT=Figure10.OutputofanAD9834witha50MHzmasterDoyouhavetoolsthatmakeiteasiertoprogramandpredicttheperformanceoftheDDS?Theon-linein ctivedesigntoolisanassistantforselectingtuningwords,givenareferenceclockanddesiredoutputfrequenciesand/orphases.Therequiredfrequencyischosen,andidealizedoutputharmonicsareshownafteranexternal

Figure11.Screenpresentationprovidedbyanin ctivedesigntool.Asinx/xpresentationofatypicaldevicereconstructionfilterhasbeenapplied.AnexampleisshowninFigure11.Tabulardataisalsoprovidedforthemajorimagesandharmonics.HowwillthesetoolshelpmeprogramtheAllthat’sneededistherequiredfrequencyoutputandthesystem’sreferenceclockfrequency.Thedesigntoolwilloutputthefullprogrammingsequencerequiredto Figure12.Typicaldisyofprogrammingthepart.IntheexampleinFigure12,theMCLKissetto25MHzandthedesiredoutputfrequencyissetto10MHz.Oncetheupdatebuttonispressed,thefullprogrammingsequencetoprogramthepartiscontainedintheInitSequenceregister.HowcanIevaluateyourDDSdevices?AllDDSdeviceshaveanevaluationboardavailableforpurchase.Theycomewithdedicatedsoftware,allowingtheusertotest/evaluatetheparteasilywithinminutesofre