Altera原版文章：数字预矫正

DigitalPredistortionAgendaIntroductionAlgorithmStandardlookuptablemethodPhaserelatederrorsMemoryeffectImplementationMultipliersMemoryCordicProcessorsIntroduction:PurposeTechnologydemonstratorShowDPDcanbedoneefficientlyonPLDProvidestartingpointfordesignShowefficientimplementationofkeycomponentsProvideFPGAbenchmarkforcustomerdesignIntroduction:PredistortionVRFVinVRFVinOverallLinear

ResponseVrf=kVinVRFVinPAVrf=kVinIdealPAVdVPAPAVrf=fnlkVdRealPADPDVd=1/fnlVinVdVinPredistorterAlgorithms:OverviewAdaptiveLookupTable(LUT)LookuptableforphaseandmagnitudecorrectionvaluesDealswithmagnitudedependenterrorsVolterramodellingofPADirectimplementationIndirectLUTimplementationAlgorithm:DistanceGradientMethodAssumption:Erroronlydependsonmagnitudeφ

arctan(I/Q)LUT

(∆r&∆φ)I&Q

Demodaddressr

(I2+Q2)1/2φ

arctan(I/Q)r

(I2+Q2)1/2delaydelayQ

r*cos(φ)I

r*sin(φ)I&Q

modPAI,QinI,Qout·(-1)·(-1)Algorithm:DistanceGradientMethodMATLABsimulationresultsusingSALEHPAmodelEVMimprovedinregionof90%Dist–GradientLUTFreqPlots

PredistortionimprovesACLRby70dB(considering700-900and1100-1300asside-bandregionsformeasurements)Simplifiedsimulationenvironment(usingSALEHPAmodel)Algorithm:PhaserelatederrorAddsdimensiontolookuptableIncreasesmemory,logicsamesizeasbeforeIncreasestimetoconvergeLUTcontent,LUTcontent,WithoutphaseerrorcompensationWithphaseerrorcompensationAlgorithm:MemoryeffectModelseffectofshorttermtemperatureincreaseonsiliconThreepossibleapproachesAdd“deltalook-uptable”(Intersilsolution)AddnewdimensiontoLUT(fullyadaptive)UseFIRinmagnitudeaddresscalculationAlgorithm:MemoryeffectPAmodels:Saleh[1]Memoryless,ErrorsonlydependentoninputmagnitudeVolterrabased,withorwithoutmemory:[2,3]Errordependoninputmagnitudeandphase[1]A.SalehandJ.Salz,AdaptiveLinearizationofPowerAmplifiersinDigitalRadioSystems,BellSyst.Tech.J.,Vol.62,No.4,pp1019-1033,Apr.1983[2]L.Ding,G.T.Zhou,D.R.Morgan,Z.Ma,J.S.Kenney,J.KirnandC.R.Giardina,Memorypolynomialpredistorterbasedontheindirectlearningarchitecture,Proc.IEEEGlobalTelecommunicationsConference,Taipei,Taiwan,Nov.2002[3].H.Qian,andG.T.Zhou,"Aneuralnetworkpredistorterfornonlinearpoweramplifierswithmemory,"Proc.10thIEEEDSPWorkshop(DSP’2002),PineMountain,GA,October2002Algorithm:MemoryeffectErrormechanism:ErrordependsontemperatureTemperaturedependsonpreviousmagnitudesNewPAmodel:AlteramodelErrordependsoncurrentandpreviousmagnitudesErrorindependentofinputphaseSolutionFIRfilterinaddresscalculationφ

arctan(I/Q)LUT

(∆I&∆Q)I&QDemodaddressr

(I2+Q2)1/2φ

arctan(I/Q)r

(I2+Q2)1/2delay∆I=∆r*sin(∆φ)∆Q=∆r*cos(∆φ)I&Q

modPAI,QinI,Qout·(-1)·(-1)delayFIRProcessor+hardwareaccelerationPredistortionReferenceDesignDSPBlocksSyncNCOFIRDSPBlockArchitecture&Resources+OptionalPipeliningOutputRegistersOutputMUX+-S+-SInputRegistersHighPerformanceDSPOperation18x18Functionsat282MHzInput,Output&PipeliningregistersReduceoverallLogicusageAdd/Accumulate/SubtractSigned&unsignedoperationsDynamicallychangebetweenAdd&Subtract

Supportcomplexmultiplications(Ar+jAi)x(Br+jBi)=(ArBr–AiBi)+j(AiBr+

ArBi)4Multiplications,1Addition&1Subtraction

···

·

-

+φ

arctan(I/Q)LUT

(∆I&∆Q)I&QDemodaddressr

(I2+Q2)1/2φ

arctan(I/Q)r

(I2+Q2)1/2delay∆I=∆r*sin(∆φ)∆Q=∆r*cos(∆φ)I&Q

modPAI,QinI,Qout·(-1)·(-1)delayFIRProcessor+hardwareaccelerationPredistortionReferenceDesignDSPBlocksRAMSyncNCOFIRTriMatrix™MemoryToday’sapplicationsneedmorehighperformancememoryOnesizedoesnotfitallWidechoiceofmodesandwidthsM512BlocksM4KBlocksM-RAMExternalMemoryDevicesDDRSDRAM&SRAMSDRSDRAMQDR&QDRIISRAMZBTSRAMDDRFCRAMTrueDualPortRAMEmbeddedShiftRegisterMode512KbitsOperatesUpto300MhzTrueDualPortRAMEmbeddedShiftRegisterModeOperatesUpto312MhzRateChangingEmbeddedShiftRegisterModeOperatesUpto312MhzMoreBitsForLargerMemoryBufferingMoreDataPortsforGreaterMemoryBandwidthφ

arctan(I/Q)LUT

(∆I&∆Q)I&QDemodaddressr

(I2+Q2)1/2φ

arctan(I/Q)r

(I2+Q2)1/2delay∆I=∆r*sin(∆φ)∆Q=∆r*cos(∆φ)I&Q

modPAI,QinI,Qout·(-1)·(-1)delayFIRProcessor+hardwareaccelerationPredistortionReferenceDesignDSPBlocksRAMCORDICSyncNCOFIRCORDICHardwareefficientalgorithmforcomputingfunctionssuchas:TrigonometricHyperbolicLogarithmicIterativesolutionthatusesonlyshiftsandadding/subtractingHighperformanceasnomultiplicationsanddivisionsSimple/lesshardwarerequiredAlteraCORDICsolutionforDPDCORDICX_inY_inZ_inmodeX_outY_outZ_out

CartesiantoPolarconversion

X_in,Y_in=Cartesianvalues,Z_in=0,mode=0

X_out=magnitude,Z_out=phasePolartoCartesianconversionX_in=magnitude,Z_in=phase,Y_in=0,mode=1X_out,Y_out=CartesianvaluesModeselectsconversiondirectionPipelinedenablingnewinputstobeappliedineveryclkcycleAfterinitiallatencyvalidoutputswillappearoneveryclkcycleTimesharing:oneachclkcyclethemodeoftheCORDICcanbechangedCORDICArchitectureQuadrantdetect&IPmodifyAdd/Sub&ShiftRegQuadrantAdjustIteration1Iterationn

ParallelArchitectureenablinghighperformanceCORDICalgorithmcanonlydealwithvectorrotationsof–90to+90degreesRequireadditionallogic(Quadrantblocks)tobeabletodealwithvectorsinanyofthefourquadrants

Parameterisablecodeinputvectorwidthsandnumberofiterationscanbechanged.CORDICImplementationLEsinAltera

PLDsEachLEissuitedforimplementingtherequiredadders/subtractors.LEscandynamicallychangefromoperatingasanaddertosubtractorEachLEcontainsaregisterPerformanceVectorWidthsIterationsFmaxLEsrequiredAbsno.%oftotalin1S101616219MHz130012%3232189MHz460043%φ

arctan(I/Q)LUT

(∆I&∆Q)I&QDemodaddressr

(I2+Q2)1/2φ

arctan(I/Q)r

(I2+Q2)1/2delay∆I=∆r*sin(∆φ)∆Q=∆r*cos(∆φ)I&Q

modPAI,QinI,Qout·(-1)·(-1)delayFIRProcessor+hardwareaccelerationPredistortionReferenceDesignDSPBlocksRAMCORDICSyncNCOFIRImplementation:Processor?Shouldweuseprocessor?ForFlexibilityEasytoaddcustominterpolationorsimilarLowdatarateinfeedbackpathatbasebandAgainstStraightforwarddatapath(few“IF”branches)TooslowatIFNoclearsizeadvantageDifficulttoexploitdeeplypipelinedCORDICPerformance(DhrystoneMIPS2.1)20501002000SoftCoreHardCore

SoftCoreAdvantagesFlexibilityLowCostPortableDesignScalabilityObsolescenceProofFitsBroadRangeofAlteraPLDFamilies

HardCoreAdvantagesHighPerformance922TDMITime-to-MarketLotsofOn-ChipMemoryLeverageLargeExistingCodeBaseExcalibur™EmbeddedProcessorCoresImplementationForwardpath:I,QmultipliersLookuptable:DualportmemoryFeedbackpathNioswithcustominstructionsCORDICaccelerationMultiplyaccelerationTargetdevicesStratix-ContainsDSPBlocksTriMatrixRAMallowsforLargelookuptables(multipledimensions)Suitableifup/downconvertersarealsointegratedCyclone-ExtensiveuseofCORDICLowestcostRefDesignResourceUtilisationEstimates5000LEs(50%ofavailin1S10)4DSPblocks(67%ofavailin1S10)3M4KRAMblocks(5%ofavailin1S10)2M512RAMblocks(2%ofavailin1S10)Assumes18bitwideI/Q,64deepX32bitwideLUT.Therefdesignonlycontainstheadaptivelookuptablealgorithm.SOPC3.0BuilderBuildaCustomCompanionChipforYourProcessor-BasedSystemWithSOPCBuilderInterfacetoPopularMicroprocessorsPowerPCTIDSPPCICustomPeripheralContentCommunicationsIPSignalProcessingAlgorithmsMemoryInterfacesHardwareAccelerationFunctionsSecurityIPImageProcessingTrafficManagement/RoutingAlgorithmsSummaryReferencedesignbasedonlookuptablesonStratix1S10WorksformemorylessPACompensatesformemoryeffectAssumption:ErrorsindependentofphaseCanbetunedandmodifiedOpenSource–extractkeycomponents,leavetherest

Discussion…DevelopmentToolsQuartusIIRobust,stabletoolforblock-baseddesignIncludeseverythingyouneedtobuildSOPCdesignsInterfacestoallleading3rdpartyEDAtoolsSOPCBuilderConfiguresprocessors,busarchitectures,IPandfirmwareinonesimpleenvironmentInterfacestoNios,XAfamily&popularMicroprocessorfamiliesDSPBuilderWorkswithMATLAB/SimulinktoprovideanFPGAdevelopmentenvironmentthatisidealforsystemsengineersWorkswithSOPCBuildertogiveaC-basedDSPdesignflowWhat