EDA数字时钟设计报告

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EDA课程设计报告设计题目：数字时钟班级：姓名：学号：日期：系统设计要求设计一个具有整点报时功能的数字时钟，要求；1.具有时、分、秒的计数显示功能，24小时循环显示。2.具有清零、预置初值功能，实现LED动态显示，整点报时采用声音报时。3.采用元件例化方式实现各模块间的连接。系统设计方案要设计的数字时钟具有基本的计时功能，采用二十四小时计时，显示时分秒，其中分钟和秒模块采用60进制计数器实现，小时模块则需要一24进制计数器实现。要实现时钟预置初值功能分别设计一个分钟允许置数端和小时允许置数端。要实现LED动态显示，单独设计一个显示模块。整点报时采用隔秒响一声实现。最后通过元器件例化将各个模块连接起来。六十进制计数器模块二十四进制计数器模块显示模块元器件例化模块主要VHDL源程序六十进制计数器模块LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYliushijinzhiISPORT(clk,clr,en,a:INSTD_LOGIC;load_1,load_10:INSTD_LOGIC_VECTOR(3DOWNTO0);co:OUTSTD_LOGIC;q_10,q_1:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDliushijinzhi;ARCHITECTUREbehavOFliushijinzhiISSIGNALq1:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALq10:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALc:STD_LOGIC;BEGINPROCESS(clk,clr,a,en,load_1)BEGINIF(clr='1')THENq1<="0000";ELSIF(a='1')THENq1<=load_1;ELSIF(clk'eventANDclk='1')THENIF(en='1')thenIF(q1="1001")THENq1<="0000";c<='0';ELSIF(q1="1000")THENq1<=q1+'1';c<='1';ELSEq1<=q1+'1';c<='0';ENDIF;ENDIF;ENDIF;ENDPROCESS;PROCESS(c,clk,clr,a,load_10)BEGINIF(clr='1')THENq10<="0000";ELSIF(a='1')THENq10<=load_10;ELSIF(clk'eventANDclk='1')THENIF(c='1')THENIF(q10="0101")THENq10<="0000";co<='1';ELSEq10<=q10+'1';co<='0';ENDIF;ENDIF;ENDIF;ENDPROCESS;PROCESS(q1)BEGINCASEq1ISWHEN"0000"=>q_1<="1111110";WHEN"0001"=>q_1<="0110000";WHEN"0010"=>q_1<="1101101";WHEN"0011"=>q_1<="1111001";WHEN"0100"=>q_1<="0110011";WHEN"0101"=>q_1<="1011011";WHEN"0110"=>q_1<="0011111";WHEN"0111"=>q_1<="1110000";WHEN"1000"=>q_1<="1111111";WHEN"1001"=>q_1<="1110011";WHENOTHERS=>q_1<="ZZZZZZZ";ENDCASE;ENDPROCESS;PROCESS(q10)BEGINCASEq10ISWHEN"0000"=>q_10<="1111110";WHEN"0001"=>q_10<="0110000";WHEN"0010"=>q_10<="1101101";WHEN"0011"=>q_10<="1111001";WHEN"0100"=>q_10<="0110011";WHEN"0101"=>q_10<="1011011";WHENOTHERS=>q_10<="ZZZZZZZ";ENDCASE;ENDPROCESS;ENDbehav;二十四进制计数器模块LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYershisijinzhiISPORT(clk,clr,en,a:INSTD_LOGIC;load_1,load_10:INSTD_LOGIC_VECTOR(3DOWNTO0);q_1,q_10:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDershisijinzhi;ARCHITECTUREbehavOFershisijinzhiISSIGNALc:STD_LOGIC;SIGNALq1:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALq10:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(clk,clr,en,a,load_1)BEGINIF(clr='1')THENq1<="0000";ELSIF(a='1')THENq1<=load_1;ELSIF(clk'eventANDclk='1')THENIF(q1="0011"ANDq10="0010")THENq1<="0000";ELSIF(en='1')THENIF(q1="1001")THENq1<="0000";c<='0';ELSIF(q1="1000")THENq1<=q1+'1';c<='1';ELSEq1<=q1+'1';c<='0';ENDIF;ENDIF;ENDIF;ENDPROCESS;PROCESS(clk,clr,c,a,q1,load_10)BEGINIF(clr='1')THENq10<="0000";ELSIF(a='1')THENq10<=load_10;ELSIF(clk'eventANDclk='1')THENIF(q1="0011"ANDq10="0010")THENq10<="0000";ELSIF(c='1')THENIF(q10="0010")THENq10<="0000";ELSEq10<=q10+'1';ENDIF;ENDIF;ENDIF;ENDPROCESS;PROCESS(q1)BEGINCASEq1ISWHEN"0000"=>q_1<="1111110";WHEN"0001"=>q_1<="0110000";WHEN"0010"=>q_1<="1101101";WHEN"0011"=>q_1<="1111001";WHEN"0100"=>q_1<="0110011";WHEN"0101"=>q_1<="1011011";WHEN"0110"=>q_1<="0011111";WHEN"0111"=>q_1<="1110000";WHEN"1000"=>q_1<="1111111";WHEN"1001"=>q_1<="1110011";WHENOTHERS=>q_1<="ZZZZZZZ";ENDCASE;ENDPROCESS;PROCESS(q10)BEGINCASEq10ISWHEN"0000"=>q_10<="1111110";WHEN"0001"=>q_10<="0110000";WHEN"0010"=>q_10<="1101101";WHENOTHERS=>q_10<="ZZZZZZZ";ENDCASE;ENDPROCESS;ENDbehav;显示模块LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYqdmkzISPORT(clk,clr:INSTD_LOGIC;din1,din2,din3,din4,din5,din6:INSTD_LOGIC_VECTOR(6DOWNTO0);sel:OUTSTD_LOGIC_VECTOR(2DOWNTO0);num:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDqdmkz;ARCHITECTUREbehavOFqdmkzISSIGNALq:STD_LOGIC_VECTOR(2DOWNTO0);BEGINsel<=q;PROCESS(clk,clr)BEGINIF(clr='1')THENq<="101";ELSIF(clk'eventANDclk='1')THENIF(q="000")THENq<="101";ELSEq<=q-'1';ENDIF;ENDIF;ENDPROCESS;PROCESS(q,din1,din2,din3,din4,din5,din6)BEGINCASEqISWHEN"101"=>num<=din1;WHEN"100"=>num<=din2;WHEN"011"=>num<=din3;WHEN"010"=>num<=din4;WHEN"001"=>num<=din5;WHEN"000"=>num<=din6;WHENOTHERS=>num<="ZZZZZZZ";ENDCASE;ENDPROCESS;ENDbehav;元器件例化模块含报时LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYshuzishizhongISPORT(clk1,clk2,clrh,clrm,clrs,clr,ah,am,as,en:INSTD_LOGIC;load_1,load_10:INSTD_LOGIC_VECTOR(3DOWNTO0);sel:OUTSTD_LOGIC_VECTOR(2DOWNTO0);num:OUTSTD_LOGIC_VECTOR(6DOWNTO0);alm:OUTSTD_LOGIC);ENDshuzishizhong;ARCHITECTUREoneOFshuzishizhongISCOMPONENTliushijinzhiISPORT(clk,clr,en,a:INSTD_LOGIC;load_1,load_10:INSTD_LOGIC_VECTOR(3DOWNTO0);co:OUTSTD_LOGIC;q_10,q_1:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDCOMPONENT;COMPONENTershisijinzhiISPORT(clk,clr,en,a:INSTD_LOGIC;load_1,load_10:INSTD_LOGIC_VECTOR(3DOWNTO0);q_1,q_10:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDCOMPONENT;COMPONENTqdmkzISPORT(clk,clr:INSTD_LOGIC;din1,din2,din3,din4,din5,din6:INSTD_LOGIC_VECTOR(6DOWNTO0);sel:OUTSTD_LOGIC_VECTOR(2DOWNTO0);num:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDCOMPONENT;SIGNALco1,co2:STD_LOGIC;SIGNALsq_1,sq_10,mq_1,mq_10,hq_1,hq_10:STD_LOGIC_VECTOR(6DOWNTO0);BEGINu1:liushijinzhiPORTMAP(clk1,clrs,en,as,load_1,load_10,co1,sq_10,sq_1);u2:liushijinzhiPORTMAP(co1,clrm,en,am,load_1,load_10,co2,mq_10,mq_1);u3:ershisijinzhiPORTMAP(co2,clrh,en,ah,load_1,load_10,hq_1,hq_10);u4:qdmkzPORTMAP(clk2,clr,hq_10,hq_1,mq_10,mq_1,sq_10,sq_1,sel,num);PROCESS(sq_10,sq_1,mq_10,mq_1,hq_10,hq_1)BEGINIF(((hq_10="1111110"ANDhq_1="1111110")OR(hq_10="0110000"ANDhq_1="1101101"))ANDmq_1="1111110"ANDmq_10="1111110"AND((sq_10="1111110"AND(sq_1="1111110"ORsq_1="1101101"ORsq_1="0110011"ORsq_1="0011111"ORsq_1="1111111"))OR(sq_10="0110000"AND(sq_1="1111110"ORsq_1="1101101"ORsq_1="0110011"ORsq_1="0011111"ORsq_1="1111111"))OR(sq_10="1101101"AND(sq_1="1111110"ORsq_1="1101101"))))THENalm<='1';ELSIF(((hq_10="1111110"ANDhq_1="0110000")OR(hq_10="0110000"ANDhq_1="1111001"))ANDmq_1="1111110"ANDmq_10="1111110"ANDsq_10="1111110"ANDsq_1="1111110")THENalm<='1';ELSIF(((hq_10="1111110"ANDhq_1="1101101")OR(hq_10="0110000"ANDhq_1="0110011"))ANDmq_1="1111110"ANDmq_10="1111110"ANDsq_10="1111110"AND(sq_1="1111110"ORsq_1="1101101"))THENalm<='1';ELSIF(((hq_10="1111110"ANDhq_1="1111001")OR(hq_10="0110000"ANDhq_1="1011011"))ANDmq_1="1111110"ANDmq_10="1111110"ANDsq_10="1111110"AND(sq_1="1111110"ORsq_1="1101101"ORsq_1="0110011"))THENalm<='1';ELSIF(((hq_10="1111110"ANDhq_1="0110011")OR(hq_10="0110000"ANDhq_1="0011111"))ANDmq_1="1111110"ANDmq_10="1111110"ANDsq_10="1111110"AND(sq_1="1111110"ORsq_1="1101101"ORsq_1="0110011"ORsq_1="0011111"))THENalm<='1';ELSIF(((hq_10="1111110"ANDhq_1="1011011")OR(hq_10="0110000"ANDhq_1="1110000"))ANDmq_1="1111110"ANDmq_10="1111110"ANDsq_10="1111110"AND(sq_1="1111110"ORsq_1="1101101"ORsq_1="0110011"ORsq_1="0011111"ORsq_1="1111111"))THENalm<='1';ELSIF(((hq_10="1111110"ANDhq_1="0011111")OR(hq_10="0110000"ANDhq_1="1111111"))ANDmq_1="1111110"ANDmq_10="1111110"AND((sq_10="1111110"AND(sq_1="1111110"ORsq_1="1101101"ORsq_1="0110011"ORsq_1="0011111"ORsq_1="1111111"))OR(sq_10="0110000"ANDsq_1="1111110")))THENalm<='1';ELSIF(((hq_10="1111110"ANDhq_1="1110000")OR(hq_10="0110000"ANDhq_1="1110011"))ANDmq_1="1111110"ANDmq_10="1111110"AND((sq_10="1111110"AND(sq_1="1111110"ORsq_1="1101101"ORsq_1="0110011"ORsq_1="0011111"ORsq_1="1111111"))OR(sq_10="0110000"AND(sq_1="1111110"ORsq_1="1101101"))))THENalm<='1';ELSIF(((hq_10="1111110"ANDhq_1="1111111")OR(hq_10="1101101"ANDhq_1="1111110"))ANDmq_1="1111110"ANDmq_10="1111110"AND((sq_10="1111110"AND(sq_1="1111110"ORsq_1="1101101"ORsq_1="0110011"ORsq_1="0011111"ORsq_1="1111111"))OR(sq_10="0110000"AND(sq_1="1111110"ORsq_1="1101101"ORsq_1="0110011"))))THENalm<='1';ELSIF(((hq_10="1111110"ANDhq_1="1110011")OR(hq_10="1101101"ANDhq_1="0110000"))ANDmq_1="1111110"ANDmq_10="1111110"AND((sq_10="1111110"AND(sq_1="1111110"ORsq_1="1101101"ORsq_1="0110011"ORsq_1="0011111"ORsq_1="1111111"))OR(sq_10="0110000"AND(sq_1="1111110"ORsq_1="1101101"ORsq_1="0110011"ORsq_1="0011111"))))THENalm<='1';ELSIF(((hq