集成电路设计-时序逻辑电路设计

1集成电路设计第七章

时序逻辑电路设计

DesigningSequentialLogicCircuits2纲要基本概念组合逻辑与时序逻辑电路有限状态机（FSM）LatchversusRegister锁存器寄存器动态锁存器/寄存器时钟控制寄存器C2MOS流水线非双稳态时序电路时序问题3LogicCircuits:

(1)CombinationalLogic

(2)SequentialLogic7-1基本概念

4Itismemoryless;i.e.,withoutstates.CombinationalCircuitsInputOutputCombinationalLogic

5CombinationalLogic

DesignProcedures1.Constructthetruthtable2.Basedonthetruthtable (a)Simplifythelogicandimplementby (i)randomlogicgates (ii)multiplexers (iii)PLA’sorPAL’s (b)ImplementthecircuitbyROM’s6——SequentialLogicSequentialLogicAsynchronousCircuitsSynchronousCircuits7Duetothetimedelayproblems(races,hazards,…etc.)peoplerarelydesignsequentialcircuitsinasynchronousapproach.Synchronouscircuitsneedasystemclocktostrobethewholesystem.Itiseasiertocontroltheinputsandstates.Thespeedmaybeslowerinthesynchronouscircuits.8CombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsDQFiniteStateMachine（FSM)9ExternalinputsandstatesastheinputsOutputs，andNextstateClock，edgesensitive（positiveornegative）MealyversusMoorestatemachines10MooremachineFF—Flip-Flop

outputdependsonlyonthecurrentstateZ=f(y)potentialimplementationadvantagesinspeedandsize；initialstateFFCombinationalLogicYyXZCLK11Mealymachineboththeinputandthecurrentstateisusedtodeterminetheoutput

Z=f(x,y)

Y=f

(x,y)XyCombinationalCircuitsFFCLKZY12SixDesign-StepProcessesforFSM1.Understandthestatementofthespecification2.ObtainanabstractspecificationoftheFSM3.Performastateminimization4.Performstateassignment5.ChooseFFtypestoimplementFSMstateregister6.ImplementtheFSM13StaticvsDynamicStorageStaticstoragepreservestateaslongasthepowerisonhavepositivefeedback(regeneration)withaninternalconnectionbetweentheoutputandtheinputusefulwhenupdatesareinfrequent(clockgating)Dynamicstoragestorestateonparasiticcapacitorsonlyholdstateforshortperiodsoftime(milliseconds)requireperiodicrefreshusuallysimpler,sohigherspeedandlowerpower14Latchesvs

FlipflopsLatcheslevelsensitivecircuitthatpassesinputstoQwhentheclockishigh(orlow)-transparentmodeinputsampledonthefallingedgeoftheclockisheldstablewhenclockislow(orhigh)-holdmodeFlipflops(edge-triggered)一般指触发器edgesensitivecircuitsthatsampletheinputsonaclocktransitionpositiveedge-triggered:01

negativeedge-triggered:10builtusinglatches(e.g.,master-slaveflipflops)15LatchversusRegisterLatch storesdatawhenclockislowRegister storesdatawhenclockrisesDClkQClkDQDClkQClkDQTransparent167-2锁存器（Latches）类型Latch-BasedDesign时间定义与约束改变输出多路开关型锁存器17类型18Latch-BasedDesign—forsequentialNlatchistransparent

whenf=0Platchistransparent

whenf=1PLatchLogicLogicNLatchf19时间定义（TimingDefinitions）tCLKtDtc-qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQtsuSetup建起时间——时钟翻转之前数据必须有效的时间；thold

维持时间——时钟触发之后数据仍然有效的时间；tc-q

传播延迟时间——CLK到Q20CharacterizingTimingRegisterLatchClkDQtC-QClkDQtC-QtD-Q21约束（SystemTimingConstraints）约束1： 最小时钟周期：T

tc-q+tplogic+tsu一个CLK周期必须容纳任何一级电路的最大延迟时间tplogicCombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsT(clockperiod)22约束2寄存器维持时间：tholdtcd-register+tcd-logic

tholdtcd-register

寄存器最小传播延迟cd---ContaminationDelaytcd-logic逻辑电路最小传播延迟保证时序元件的输入数据在CLK边沿之后能够维持足够的时间，不会因为新进入的数据流而过早改变。tCLKtDtc-qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQ23PositiveFeedback:Bi-Stabilitycascadedinverters24VTCVo1Vi25Vo1Vi25Vo1Vi1ACBVo2Vi1=Vo2Vo1Vi2Vi2=Vo1Ifthegaininthetransientregionislargerthan1,onlyAandBarestableoperationpoints.Cisameta-stableoperationpoint.25Meta-StabilityGainshouldbelargerthan1inthetransitionregion====26BistableCircuits（flip-flops）改变输出cuttingthefeedbackloop(muxbasedlatch)overpoweringthefeedbackloop(asusedinSRAMs)Vi1Vi227WritingintoaStaticLatchDCLKCLKDConvertingintoaMUXForcingthestate(canimplementasNMOS-only)Usetheclockasadecouplingsignal,thatdistinguishesbetweenthetransparentandopaquestates弱输出28多路开关型锁存器

（Mux-BasedLatches）Negativelatch(transparentwhenCLK=0)Positivelatch(transparentwhenCLK=1)CLK10DQ0CLK1DQ29Mux-BasedLatch

传输阶段（透明）维持阶段30Mux-BasedLatchNMOSonlyNon-overlappingclocks317-3寄存器主从式边沿触发寄存器降低时钟负载非理想时钟—时钟重叠静态RS触发器—强信号写数据32Master-Slave(Edge-Triggered)RegisterTwooppositelatchestriggeronedgeAlsocalledmaster-slavelatchpair

33Master-SlaveRegisterMultiplexer-basedlatchpair34多路开关型寄存器的时序特性寄存器时序参数SetupTime,HoldTime,PropagationDelayassume：反相器传播延迟:tinv

传输门传播延迟:tTG

Clkinverter:

tclk-int

=0tCLKtDtc-qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQ35TimingofRegisterSetupTimeData在Clk上升沿前必须有效的时间—QM稳定时间传播路径：Inv1—

TG1—

Inv3—

TG2Tsetup

=

3tinv+tTG

PropagationDelayTc-q

—

QM传播到输出的时间传播路径：TG3—

Inv6Tc-q

=tTG

+tinv

HoldTimeClk上升沿之后输入必须保持稳定的时间TG1关断Thold

=

036CharacterizingTimingRegisterLatchClkDQtC-QClkDQtC-QtD-Q37降低时钟负载（ReducedClockLoad）

设计复杂性提高（I2、I4强度）反向传导

(可能影响前级存储结果）38时钟偏差（ClockSkew）

——时钟重叠（

ClockOverlap）CLKCLKAB(a)Schematicdiagram(b)OverlappingclockpairsXDQCLKCLKCLKCLK

时钟变为上升沿时，从级应为维持状态；由于时钟重叠，D与Q之间形成直接通路；产生竞争：A同时被D、B驱动；减弱B的强度；输出不确定状态。

clkskew产生原因？39伪静态两相D寄存器——不重叠时钟两相时钟；时间间隔足够长；伪静态—保持时间长，漏电影响；不会产生重叠。CLK1CLK1ABXDQCLK2CLK2CLK2CLK140静态RS触发器—强信号写数据（OverpoweringtheFeedbackLoop

─Cross-CoupledPairs）NOR-basedset-reset41Cross-CoupledNANDCross-coupledNANDsAddedclockThisisnotusedindatapathsanymore,

butisabasicbuildingmemorycell427-4动态锁存器/寄存器DCLKCLKQDynamic(charge-based)StaticStorageMechanisms43StaticvsDynamicStorageStaticstoragepreservestateaslongasthepowerisonhavepositivefeedback(regeneration)withaninternalconnectionbetweentheoutputandtheinputusefulwhenupdatesareinfrequent(clockgating)Dynamicstoragestorestateonparasiticcapacitorsonlyholdstateforshortperiodsoftime(milliseconds)requireperiodicrefreshusuallysimpler,sohigherspeedandlowerpower44动态边沿触发寄存器CLKCLKQDCLKCLKSetupTime传播路径：TG1Tsetup=tTG

PropagationDelay传播路径：Inv1—TG2—Inv3Tc-q=tTG+2tinv

HoldTimeThold=045MakingaDynamicLatchPseudo-Static针对噪声干扰和漏电影响；伪静态—弱反馈；增加延时，提高抗干扰能力。467-5时钟控制寄存器C2MOS

——时钟偏差不敏感方法“Keepers”canbeaddedtomakecircuitpseudo-static主从式；正沿触发；CLK=0时X=D求值，从级维持（高阻态）；CLK=1时相反。只要时钟边沿的上升和下降时间足够小，对时钟重叠不敏感。47InsensitivetoClock-OverlapM1DQM4M200VDDXM5M8M6VDD(a)(0-0)overlapM3M1DQM21VDDXM71M5M6VDD(b)(1-1)overlap487-6真单相时钟寄存器

（TrueSinglePhaseClockRegister）Negativelatch(transparentwhenCLK=0)Positivelatch(transparentwhenCLK=1)无时钟重叠；减少时钟负载。49IncludingLogicinTSPCANDlatchExample:logicinsidethelatch可嵌入逻辑功能。50TSPCRegisterCLK=0X=反相的D，Y预充电，Q维持；CLK=1X高阻，Y=X的反相，Q=Y。51Pulse-TriggeredLatchesMaster-SlaveLatchesDClkQDClkQClkDataDClkQClkDataPulse-TriggeredLatchL1L2LWaystodesignanedge-triggeredsequentialcell:52PulsedLatches537-7流水线（Pipelining）ReferencePipelined寄存器传播延迟寄存器建立时间组合逻辑最坏延迟54Latch-BasedPipeline557-8非双稳态时序电路

Non-BistableSequentialCircuitsSchmittTriggerMonostableTriggerAstable

MultivibratorsVCO56SchmittTrigger对于缓慢的输入，快速翻转的输出响应；VTC正向、负向变化的输入信号有不同的阈值；滞回电压为其差；用于提高抗干扰能力，减少振铃现象。InOutVinVoutVOHVOLVM–VM+57NoiseSuppressionusingSchmittTrigger58CMOSSchmittTriggerMovesswitchingthresholdofthefirstinverter反相器等效晶体管比：β1/（β

2+β

4）开关阈值提高反相器等效晶体管比：（β

1+β

3）/β2开关阈值降低59MultivibratorCircuitsBistable

MultivibratorMonostable

MultivibratorAstable

Multivibratorflip-flop,SchmittTriggerone-shotoscillatorSRT60Transition-TriggeredMonostableDELAYtdInOuttd61MonostableTrigger(RC-based)VDDInOutABCRInBOuttVMt2t1(a)Triggercircuit.(b)Waveforms.62Astable

Multivibrators(Oscillators)RingOscillator奇数个反相器T=2N*tpsimulatedresponseof5-stageoscillator012N-163RelaxationOscillator—弛缓Out2CROut1IntI1I2T

=2(log3)RCanoscillatorinwhichacapacitorischargedgraduallyandthendischargedrapidly64VoltageControllerOscillator(VCO)InVDDM3M1M2M4M5VDDM6Vcontr

CurrentstarvedinverterIrefIrefSchmittTriggerrestoressignalslopes0.51.52.5Vcontr

(V)0.0246tpHL

(nsec)propagationdelayasafunctionofcontrolvoltage65DifferentialDelayElementandVCOin2twostageVCOv1v2v3v4VctrlVo2Vo1in1delaycell

simulatedwaveformsof2-stageVCO0.50.00.51.01.52.02.53.020.51.5V1V2V3V4time(ns)2.53.5667-9时序问题

——数据路径（Datapath）设计基本问题时序逻辑静态与动态存储同步/异步时钟偏差与抖动来源时钟偏差时钟抖动时钟分布网络时钟技术设计准则67Review:SequentialDefinitions寄存器两个电平触发latches

ofoppositetypemaster-slavechangesstateonaclockedge68Staticstorage——Dynamicstorage

Staticstorage双稳态——bistable

反馈——withfeedbacktostoreitsstate保持——preservesstateaslongasthepowerison更新数据cuttingthefeedbackpath(muxbased);overpoweringthefeedbackpath(SRAMbased)Dynamicstorage寄生电容——parasiticcapacitorsonlyaperiodoftime(milliseconds)刷新——periodicrefreshfewertransistorshigherspeedlowerpower伪静态pseudostaticduetonoise69TimingClassifications同步系统（Synchronoussystems）所有存储单元同步更新使用同步clocksignalstrictconstraintsontheclocksignalgenerationanddistributiontominimize时钟偏差Clockskew(spatialvariationsinclockedges)时钟抖动Clockjitter(temporalvariationsinclockedges)异步系统（Asynchronoussystems）自定时Self-timedsystems不需要全局时钟globallydistributedclock握手协议控制

handshaking70SynchronousTimingBasicsUnderidealconditions(i.e.,whentclk1=tclk2)T

tc-q+tplogic

+tsuthold

≤tcdlogic+tcdregUnderrealconditionsskewisconstantfromcycletocycleskewcanbepositiveornegativejittercausesTtochangeonacycle-by-cyclebasisDQR1CombinationallogicDQR2clkIntclk1tclk2tc-q,tsu,thold,tcdregtplogic,tcdlogic71SourcesofClockSkewandJitterinClockNetworkPLL1243567clockgenerationclockdriverspowersupplyinterconnectcapacitiveloadcapacitivecouplingtemperatureSkewmanufacturingdevicevariationsinclockdriversinterconnectvariationsenvironmentalvariations(powersupplyandtemperature)Jitterclockgenerationcapacitiveloadingandcouplingenvironmentalvariations(powersupplyandtemperature)72PositiveClockSkew

>0:Improvesperformance,butmakestholdhardertomeet.Iftholdisnotmet(raceconditions).T+

tc-q+tplogic

+tsu

soT

tc-q+tplogic

+tsu

-thold+≤tcdlogic+tcdreg

sothold≤tcdlogic+tcdreg

-DQR1CombinationallogicDQR2clkIntclk1tclk2delayTT+

>0+thold123473NegativeClockSkewClockanddataflowinoppositedirectionsT+

tc-q+tplogic

+tsu

soT

tc-q+tplogic

+tsu

-thold+≤tcdlogic+tcdreg

sothold≤tcdlogic+tcdreg

-DQR1CombinationallogicDQR2clkIntclk1tclk2delayTT+

<01234

<0:Degradesperformance,butthold

iseasiertomeet74ClockJitterJittercausesTtovaryonacycle-by-cyclebasisR1CombinationallogicclkIntclkT-tjitter+tjitterT-2tjitter

tc-q+tplogic

+tsu

T

tc-q+tplogic

+tsu

+2tjitterJitterdirectlyreducestheperformanceofasequentialcircuit75CombinedImpactofSkewandJitterConstraintsontheminimumclockperiod(>0)DQR1CombinationallogicDQR2Intclk1tclk2TT+

>01612-tjitterT

tc-q+tplogic

+tsu

-+2tjitter

thold

≤tcdlogic+tcdreg

––2tjitter76ClockDistributionNetworksClockskewandjitter影响性能消耗能量dynamicpower应支持时钟控制clockgating(shuttingdownunits)时钟分布技术ClockdistributionBalancedpaths(H-treenetwork,matchedRCtrees)Intheidealcase,caneliminateskewCouldtakemultiplecyclesfortheclocksignaltopropagatetotheleavesofthetreeClockgridsTypicallyusedinthefinalstageoftheclockdistributionnetworkMinimizesabsolutedelay(notrelativedelay)77H-TreeClockNetworkClockClockIdlec