基于FPGA多功能波形发生器实验报告含程序

基于FPGA的多功能波形发生器课程设计实验报告学院：电气与控制工程学院班级：微电子1101学号：1106080118姓名：李少飞日期：2015.4.2电路主体电路图各模块vhdl代码各模块仿真结果实验感悟实验主体电路各模块vhdl代码三角LIBRARYieee;USEieee.std_logic_1164.all;LIBRARYaltera_mf;USEaltera_mf.all;ENTITYsanjiaoIS PORT ( address :INSTD_LOGIC_VECTOR(7DOWNTO0); inclock :INSTD_LOGIC; q :OUTSTD_LOGIC_VECTOR(7DOWNTO0) );ENDsanjiao;ARCHITECTURESYNOFsanjiaoIS SIGNALsub_wire0 :STD_LOGIC_VECTOR(7DOWNTO0); COMPONENTaltsyncram GENERIC( clock_enable_input_a :STRING; clock_enable_output_a :STRING; init_file :STRING; intended_device_family :STRING; lpm_hint :STRING; lpm_type :STRING; numwords_a :NATURAL; operation_mode :STRING; outdata_aclr_a :STRING; outdata_reg_a :STRING; widthad_a :NATURAL; width_a :NATURAL; width_byteena_a :NATURAL ); PORT( clock0 :INSTD_LOGIC; address_a :INSTD_LOGIC_VECTOR(7DOWNTO0); q_a :OUTSTD_LOGIC_VECTOR(7DOWNTO0) ); ENDCOMPONENT;BEGIN q<=sub_wire0(7DOWNTO0); altsyncram_component:altsyncram GENERICMAP( clock_enable_input_a=>"BYPASS", clock_enable_output_a=>"BYPASS", init_file=>"sanjiao.hex", intended_device_family=>"CycloneII", lpm_hint=>"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=rom3", lpm_type=>"altsyncram", numwords_a=>256, operation_mode=>"ROM", outdata_aclr_a=>"NONE", outdata_reg_a=>"UNREGISTERED", widthad_a=>8, width_a=>8, width_byteena_a=>1 ) PORTMAP( clock0=>inclock, address_a=>address, q_a=>sub_wire0 );ENDSYN;-正弦LIBRARYieee;USEieee.std_logic_1164.all;LIBRARYaltera_mf;USEaltera_mf.all;ENTITYsinxIS PORT ( address :INSTD_LOGIC_VECTOR(7DOWNTO0); inclock :INSTD_LOGIC; q :OUTSTD_LOGIC_VECTOR(7DOWNTO0) );ENDsinx;ARCHITECTURESYNOFsinxIS SIGNALsub_wire0 :STD_LOGIC_VECTOR(7DOWNTO0); COMPONENTaltsyncram GENERIC( clock_enable_input_a :STRING; clock_enable_output_a :STRING; init_file :STRING; intended_device_family :STRING; lpm_hint :STRING; lpm_type :STRING; numwords_a :NATURAL; operation_mode :STRING; outdata_aclr_a :STRING; outdata_reg_a :STRING; widthad_a :NATURAL; width_a :NATURAL; width_byteena_a :NATURAL ); PORT( clock0 :INSTD_LOGIC; address_a :INSTD_LOGIC_VECTOR(7DOWNTO0); q_a :OUTSTD_LOGIC_VECTOR(7DOWNTO0) ); ENDCOMPONENT;BEGIN q<=sub_wire0(7DOWNTO0); altsyncram_component:altsyncram GENERICMAP( clock_enable_input_a=>"BYPASS", clock_enable_output_a=>"BYPASS", init_file=>"sinx.hex", intended_device_family=>"CycloneII", lpm_hint=>"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=ROM1", lpm_type=>"altsyncram", numwords_a=>256, operation_mode=>"ROM", outdata_aclr_a=>"NONE", outdata_reg_a=>"UNREGISTERED", widthad_a=>8, width_a=>8, width_byteena_a=>1 ) PORTMAP( clock0=>inclock, address_a=>address, q_a=>sub_wire0 );ENDSYN;方波LIBRARYieee;USEieee.std_logic_1164.all;LIBRARYaltera_mf;USEaltera_mf.all;ENTITYfangboIS PORT ( address :INSTD_LOGIC_VECTOR(7DOWNTO0); inclock :INSTD_LOGIC; q :OUTSTD_LOGIC_VECTOR(7DOWNTO0) );ENDfangbo;ARCHITECTURESYNOFfangboIS SIGNALsub_wire0 :STD_LOGIC_VECTOR(7DOWNTO0); COMPONENTaltsyncram GENERIC( clock_enable_input_a :STRING; clock_enable_output_a :STRING; init_file :STRING; intended_device_family :STRING; lpm_hint :STRING; lpm_type :STRING; numwords_a :NATURAL; operation_mode :STRING; outdata_aclr_a :STRING; outdata_reg_a :STRING; widthad_a :NATURAL; width_a :NATURAL; width_byteena_a :NATURAL ); PORT( clock0 :INSTD_LOGIC; address_a :INSTD_LOGIC_VECTOR(7DOWNTO0); q_a :OUTSTD_LOGIC_VECTOR(7DOWNTO0) ); ENDCOMPONENT;BEGIN q<=sub_wire0(7DOWNTO0); altsyncram_component:altsyncram GENERICMAP( clock_enable_input_a=>"BYPASS", clock_enable_output_a=>"BYPASS", init_file=>"fangbo.hex", intended_device_family=>"CycloneII", lpm_hint=>"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=rom2", lpm_type=>"altsyncram", numwords_a=>256, operation_mode=>"ROM", outdata_aclr_a=>"NONE", outdata_reg_a=>"UNREGISTERED", widthad_a=>8, width_a=>8, width_byteena_a=>1 ) PORTMAP( clock0=>inclock, address_a=>address, q_a=>sub_wire0 );ENDSYN;斜波LIBRARYieee;USEieee.std_logic_1164.all;LIBRARYaltera_mf;USEaltera_mf.all;ENTITYxieboIS PORT ( address :INSTD_LOGIC_VECTOR(7DOWNTO0); inclock :INSTD_LOGIC; q :OUTSTD_LOGIC_VECTOR(7DOWNTO0) );ENDxiebo;ARCHITECTURESYNOFxieboIS SIGNALsub_wire0 :STD_LOGIC_VECTOR(7DOWNTO0); COMPONENTaltsyncram GENERIC( clock_enable_input_a :STRING; clock_enable_output_a :STRING; init_file :STRING; intended_device_family :STRING; lpm_hint :STRING; lpm_type :STRING; numwords_a :NATURAL; operation_mode :STRING; outdata_aclr_a :STRING; outdata_reg_a :STRING; widthad_a :NATURAL; width_a :NATURAL; width_byteena_a :NATURAL ); PORT( clock0 :INSTD_LOGIC; address_a :INSTD_LOGIC_VECTOR(7DOWNTO0); q_a :OUTSTD_LOGIC_VECTOR(7DOWNTO0) ); ENDCOMPONENT;BEGIN q<=sub_wire0(7DOWNTO0); altsyncram_component:altsyncram GENERICMAP( clock_enable_input_a=>"BYPASS", clock_enable_output_a=>"BYPASS", init_file=>"xiebo.hex", intended_device_family=>"CycloneII", lpm_hint=>"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=rom4", lpm_type=>"altsyncram", numwords_a=>256, operation_mode=>"ROM", outdata_aclr_a=>"NONE", outdata_reg_a=>"UNREGISTERED", widthad_a=>8, width_a=>8, width_byteena_a=>1 ) PORTMAP( clock0=>inclock, address_a=>address, q_a=>sub_wire0 );ENDSYN;四选一libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitychoice_4isport(sel:instd_logic_vector(1downto0);d1,d2,d3,d4:instd_logic_vector(7downto0);q:outstd_logic_vector(7downto0));endchoice_4;architecturebehaveofchoice_4isbeginprocess(sel)begincaseseliswhen"00"=>q<=d1;when"01"=>q<=d2;when"10"=>q<=d3;when"11"=>q<=d4;whenothers=>null;endcase;endprocess;endarchitecture;2-4译码器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;ENTITYdecoder24ISPORT(sel:INstd_logic_vector(1downto0);en1,en2,en3,en4:OUTstd_logic);END;ARCHITECTUREbeOFdecoder24ISBEGINprocess(sel)BEGINcaseseliswhen"00"=>en1<='1';when"01"=>en2<='1';when"10"=>en3<='1';when"11"=>en4<='1';whenothers=>null;endcase;ENDprocess;END;正选扫描电路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;--正弦信号发生器源文件USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYsinsISPORT(CLK,en,reset:INSTD_LOGIC;--信号源时钟DOUT:OUTSTD_LOGIC_VECTOR(7DOWNTO0));--8位波形数据输出ENDsins; ARCHITECTUREbehaveOFsinsISCOMPONENTsinx--调用波形数据存储器LPM_ROM文件：datarom.vhd声明PORT(address:INSTD_LOGIC_VECTOR(7DOWNTO0);--8位地址信号inclock:INSTD_LOGIC;--地址锁存时钟q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCOMPONENT;SIGNALQ1:STD_LOGIC_VECTOR(7DOWNTO0);--设定内部节点作为地址计数器BEGINPROCESS(CLK,en,reset)--LPM_ROM地址发生器进程BEGINifreset='0'thenQ1<="00000000";elsifCLK'EVENTANDCLK='1'anden='1'THENQ1<=Q1+1;--Q1作为地址发生器计数器ENDIF;ENDPROCESS;u1:sinxPORTMAP(address=>Q1,q=>DOUT,inclock=>CLK);--例化END;斜波扫描电路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;--正弦信号发生器源文件USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYxiebosISPORT(CLK,en,reset:INSTD_LOGIC;--信号源时钟DOUT:OUTSTD_LOGIC_VECTOR(7DOWNTO0));--8位波形数据输出ENDxiebos; ARCHITECTUREbehaveOFxiebosISCOMPONENTxiebo--调用波形数据存储器LPM_ROM文件：datarom.vhd声明PORT(address:INSTD_LOGIC_VECTOR(7DOWNTO0);--8位地址信号inclock:INSTD_LOGIC;--地址锁存时钟q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCOMPONENT;SIGNALQ1:STD_LOGIC_VECTOR(7DOWNTO0);--设定内部节点作为地址计数器BEGINPROCESS(CLK,en,reset)--LPM_ROM地址发生器进程BEGINifreset='0'thenQ1<="00000000";elsifCLK'EVENTANDCLK='1'anden='1'THENQ1<=Q1+1;--Q1作为地址发生器计数器ENDIF;ENDPROCESS;u1:xieboPORTMAP(address=>Q1,q=>DOUT,inclock=>CLK);--例化END;方波扫描电路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;--正弦信号发生器源文件USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYfangbosISPORT(CLK,en,reset:INSTD_LOGIC;--信号源时钟DOUT:OUTSTD_LOGIC_VECTOR(7DOWNTO0));--8位波形数据输出ENDfangbos; ARCHITECTUREbehaveOFfangbosISCOMPONENTfangbo--调用波形数据存储器LPM_ROM文件：datarom.vhd声明PORT(address:INSTD_LOGIC_VECTOR(7DOWNTO0);--8位地址信号inclock:INSTD_LOGIC;--地址锁存时钟q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCOMPONENT;SIGNALQ1:STD_LOGIC_VECTOR(7DOWNTO0);--设定内部节点作为地址计数器BEGINPROCESS(CLK,en,reset)--LPM_ROM地址发生器进程BEGINifreset='0'thenQ1<="00000000";elsifCLK'EVENTANDCLK='1'anden='1'THENQ1<=Q1+1;--Q1作为地址发生器计数器ENDIF;ENDPROCESS;u1:fangboPORTMAP(address=>Q1,q=>DOUT,inclock=>CLK);--例化END;三角波扫描电路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;--正弦信号发生器源文件USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYsanjiaosISPORT(CLK,en,reset:INSTD_LOGIC;--信号源时钟DOUT:OUTSTD_LOGIC_VECTOR(7DOWNTO0));--8位波形数据输出ENDsanjiaos; ARCHITECTURE