Basicflow中最终版课件

16四月2024Basicflow中最终版课程目标学完这个单元后，你应该能够掌握：创建一个Milkyway库来容纳你的设计在启动ICCompiler时会读入所有必要的文件,学会解决常见的错误和警告时序分析和优化的设置能在ICCompiler进行布局、时钟树综合和布线的基本流程UnitRoadmap数据建立读入门级网表和时序约束设置时序库建立Milkyway库进行平面规划基本流程：布局时钟树综合布线分析建立时序和RC模型时序变量RC和TLU+模式延迟计算GeneralICCompilerFlowSynthesisUnit1Unit3Unit4Unit5Unit6Unit2DesignSetupDesignPlanningplace_optclock_optroute_optChipFinishingICCompiler

布局,CTS,布线及优化IPIC

Compiler门级网表平面规划布局、时钟树综合、布线及优化工艺文件TLU+模型IO放置文件(tdf)综合后网表时序约束文件SDCIOpads放置Chip/core边界Cellrows,wiretracks

建立宏单元放置输出place_optclock_optroute_optChipfinishingandDFMPowerplan标准单元放置创建时钟树完成时钟和信号线布线输出FloorplanICCompiler数据流程DEFMWDesignPlanningUnitFlow:FromSetuptoOutputLogicalDataSetupPhysicalDataSetupplace_optclock_optroute_optAnalysisOutput逻辑数据Gate-LevelNetlist(s)LogicalLibraries

.dblinkcheck_timingcreate_clock–period10...

set_input_delay–max1.2...

set_output_delay–max2.5...

set_driving_cell...

Logical(Timing)ConstraintsLogicalDataPhysicalDataplace_optclock_optroute_optAnalysis OutputLogicalData读入综合后的门级网表ICCompiler能够打开DesignCompiler生成的Milkyway数据或是DesignCompiler支持的其它格式可以读入一个或多个文件read_ddcread_verilogread_vhdl…read_verilogfile1.vfile2.v…MilkywayandDDCcanalsocontaindesignattributes!MY_TOP_DESIGN不允许相同的例化名ICCompiler不支持非唯一的设计，例如，一个设计的多个例化具有相同名字！当读入一个非唯一例化的设计，你的ICC脚本的第一个命令应该是:current_designMY_TOP_DESIGNuniquifyPARSERPARSER1PARSER2PARSER3逻辑库（.db)为所有标准单元(and,or,flipflop,…)提供时序和功能信息为硬件宏单元(IP,ROM,RAM,…)提供时序信息定义驱动/负载设计规则：最大扇出和跳变最大/最小电容进行如下指定：LogicalLibraries

.dbsetlink_library"*gates.dbio.dbrams.db"“*”=Searchalldesignsinmemory要确定所用到的单元包含正确的db!CCSLibrarySupportICCompiler支持NLDM和CCS(CompositeCurrentSource)库基于CCS模型具有更加准确的时序、噪声，功耗模型更精确的连线阻抗密勒效应动态的IR压降多电压阀温度逆增NLDM模型对于90纳米及以下是不够精确的，在90纳米及以下要用CCS模型CCSSupportedThroughoutGalaxyToolsTimingNoisePowerNanoCharPrimeTimeICCompilerDesignCompilern/aCCSSupportMilkywaySignoffDesignCompilerICCompilerGalaxyICCompiler如何查找文件?默认情况下，你必须定义所有文件的路径（不管是相对还是绝对）你可以指定到哪些路径下寻找文件：以上路径供ICCompiler用来读入或者找到文件lappendsearch_path./design_data../scriptslappendsearch_path[glob$MW_libs/*/LM]目标库与link_library和search_path变量一样，你需要定义用于映射和逻辑优化的逻辑库：默许情况，target_library只指向标准单元库settarget_library"gates.db"*逻辑参考库门级网表包含标准单元和宏单元的例化，标准单元和宏单元的时序信息被存放在逻辑参考库里Link命令将确保把所有例化单元的逻辑参考库都能找到link

risc_corenandnor

invffsdram_ifGate-LevelNetlist(s)mem.dbgates.dbip.dbpci_corelink_libraryShortcuts…import_designsorca.v\ -formatverilog\ -topORCA_TOPReplaces:read_verilog–netlistorca.vcurrent_designORCA_TOPuniquifylinksave_mw_cel–asORCA_TOPFormatcanbeverilog,db,ddc时序约束“时序约束”是用来把对设计的时序要求传达给ICCompiler应与逻辑综合用的是同一个时序约束文件（SDC）create_clock–period10[get_portsclk]

set_input_delay4–clockclk\

[get_portssd_DQ[*]]

set_output_delay5–clockclk

[get_portssd_LD]

set_load0.2[get_portspdevsel_n]

set_driving_cell–lib_cellbuf5\

[get_portspdevsel_n]

...read_sdctiming_constraints.sdcSDC=SynopsysDesignConstraints约束管理remove_sdcRemovesallSDCconstraintsremove_ideal_network-allRemovesideal_networkattributes,latenciesandtransitionsremove_annotationsRemovesallannotateddelays,transition,resistance,capacitance,checksToremoveallsettings:reset_designRemovesalloptimizationattributes(dont_touch,size_only…)andallconstraints.时序检查在PR之前，必须确保设计是被完全约束的对于没有被时序约束的路径，ICCompiler将不会对其进行优化对于缺少外部负载和驱动特性的约束，不进行检查！check_timing!check_timing报告所有没被约束的路径错误的路径同样被认为是没有被约束的下面命令是用来验证没有被约束的路径是不是OK报告设计中设置的错误路径将这些路径和check_timing报告的路径做比较report_timing_requirementscheck_timing:FalsePathsPhysicalDatacheck_physical_constraintsConstrainedand

linkeddesignPhysical

ReferenceLibraries

(Milkyway)FloorplanIPLogicalDataPhysicalDataplace_optclock_optroute_optAnalysis OutputPhysicalDataPhysicalLibraries包含标准单元和宏模块布局所必需的物理信息定义布局的unittile单元拼接referencepoint

(typically0,0)Dimension“boundingbox”Pins

(direction,layerandshape)VDDGNDABYNAND_1BlockageSymmetry(X,Y,or90º)FAbstractViewFFBUFINVNORunittile

(site)ReferenceLibraries

(Milkyway)Milkyway参考库标准单元信息储存在“视图”，例如：CEL:完整的版图视图FRAM:用于布局布线的抽象视图LM:带时序和功耗信息的逻辑模型(optional*)CEL/FRAM/and2a1and2a2….xor3a27and2a1and2a2….xor3a27VENDOR_XYZ_std_cell_90nmUsedforP&Rlib_max.dblib_min.db….LM/工艺文件(.tffile)工艺文件对每一种工艺都是唯一的包含金属层的技术参数:每个金属层/过孔的层号和命名介电常数每个金属层/过孔的物理和电气特性每个金属层/过孔的设计规则（最小线宽和最小线间距度等）各种电量的单位和精度要显示层的颜色和模式…ExampleofaTechnologyFileTechnology{ dielectric =3.7 unitTimeName ="ns" timePrecision =1000 unitLengthName ="micron" lengthPrecision =1000 gridResolution =5 unitVoltageName ="v" }...Layer"m1"{ layerNumber =16 maskName ="metal1" pitch =0.56 defaultWidth =0.23 minWidth =0.23 minSpacing =0.23 ...abc_6m.tf指定参考库通过创建一个设计库！怎样指定物理参考库和技术文件呢？create_mw_libdesign_lib_orca \ -technologytechfile.tf \ -mw_reference_library“scioram32”\ -openNowyouarereadytoapplythefloorplan…ApplyingtheFloorplanRAMSiteArrays

ArrayofplacementsitesCluster

HardBoundaryKeepouts&

PGnetsPortLocations

SignalI/OFixedCellsExample:RAMplacementread_defmy_floorplan.def–allow_physicalAllowsphysical-onlyobjectslikePGnets.CopyingtheFloorplanfromanotherMWCell

如果一个设计已经在ICCompilerorJupiterXT平面规划过，再读入相同设计的新网表，这一步是很有用的Cell_ACell_Bcopy_floorplanExistingun-floorplannedcellOpeningaMWDesignfromJupiterXTlappendsearch_path../dbsetlink_library"*gates.dbrams.db"settarget_library"gates.db"open_mw_libmy_jxt_lib.mwopen_mw_celfloorplannedset_tlu_plus_files...;explainedlaterremove_sdcread_sdcmydesign.sdcplace_optclock_optroute_optsave_mw_cel-asroutedApplyyourtimingconstraintsforP&R.检查物理约束检查库和平面规划:物理库

逻辑库不一致Core中放置单元的面积够不够狭窄布局区域的警告报告物理单元的数目、已用的sites和总利用率RC参数…可以通过manpage查看更多细节check_physical_constraints建立设计这一步做完，要保存Milkyway设计单元默认情况下，link_library,search_path,target_libraryandTLU+settings都会保存在CEL里如果库文件要移到其他地方，必须要重新设置当你重新打开CEL，默认情况下储存的设置是不会被用除非这样设置:setauto_restore_mw_cel_lib_setuptrueopen_mw_celorca_initsave_mw_cel–asorca_init保存和导入设计单元设计库DesignLibrary

design_lib_orcaTechnologyFile

abc_6m.tfMW

StandardcellsMW

MacrocellsMWPad

cellssc.dbio.dborca_initorca.vorca.sdcorca.defContainerforalldata!link_library

target_library

settingsTLU+RCmodels…morelaterUNIXStructureofaDesignMilkywayDatabase./design_lib_orca/CEL/DatabaseT.O.C,technologydataetc.….…orca_init:1SavedCellMWDesignLibraryliblib_1lib_bckUNIXManipulationofaMilkywayDatabaseUNIX%cdCELUNIX%rmORCA_placedUNIX%cp~Joes_Lib/ORCA_placed.STOP./design_lib_orca/…CEL/ORCA_initORCA_floorplannedORCA_placedORCA_ctsORCA_routedliblib_1lib_bckT.O.C.Corrupted!TestforUnderstandingListthe2variablesthatneedtobesetuptosuccessfullyreadalldesignfiles!Whatisthedifferencebetweenthelink_libraryandthetarget_library?ICCompilerrequiresachip-levelfloorplanincludingIOPADs.True/FalseAfloorplanmustalwaysbeinputtoICCompilerbyreadingaDEFfile.True/FalseWhichofthefollowingisnotrecommended?lappendsearch_pathmy_pathsetsearch_pathmy_pathsetsearch_path"$search_pathmy_path"2Minutes!SummaryGate-LevelNetlistLogicalLibrary

.dbLogicalConstraints

.sdcread_sdcread_defcheck_timing

check_physical_constraintsread_verilog/vhdl/ddcsetlink_library"*sc.db"

settarget_librarysc.dbcreate_mw_lib–technology… –mw_reference_library…IC

CompilerPhysicalConstraints

DEForMWlibraryReadyforPlace&RouteMWReferenceLibraries+techfileOr:import_designICCompilerRecommendedSetup#loadcommonsettings&usefulproceduressource../ref/icc_settings.tcllappendsearch_path./scripts../ref/sdb../ref/dbsetsymbol_library"sc_icon.sdbio_icon.sdb"setlink_library"*sc_max.dbio.dbram16x128_max.db"settarget_library"sc_max.db"create_mw_libdesign_lib_orca-open\

-technologytechfile.tf\

-mw_reference_library"mw/scmw/iomw/ram32"setmw_logic0_net"VSS"setmw_logic1_net"VDD"import_designsdesign.ddc\ -formatddc\ -topORCA_TOPread_def–allow_physicaldesign.defsave_mw_cel–overwrite #CELsavedasORCA_TOPAllsetupdonefirstandstoredin.synopsys_dc.setup.synopsys_dc.setup.synopsys_dc.setup.synopsys_dc.setup$SYNOPSYS/admin/setup~userICCstartupdirectoryUser’sSpecificProjectSetupUser’sGeneralSetupStandardSetupICCompiler3个初始化文件在.synopsys_dc.setup命令在工具打开时自动导入，导入顺序为1、2、3，且3有最高的优先级213布局阶段在布局&优化之前:不要对设计单元过约束约束要符合设计规范布局前先报告时序情况采用忽略互联线影响来查找不合实际和不正确的约束set_zero_interconnect_delay_modetrueWarning:Timerisinzerointerconnectdelaymode.(TIM-177)report_constraint–allreport_timingset_zero_interconnect_delay_modefalseInformation:Timerisnotinzerointerconnectdelaymode.(TIM-176)LogicalDataPhysicalDataplace_optclock_optroute_optAnalysis Outputplace_opt布局和优化place_opt反复执行布局和优化.

DTDP:布局的首要目标是建立时间slack为正LogicmovedclosertogetherforshorternetsCellsupsizedforoptimaldrive/speed时钟树综合设置时钟树综合时选项/例外运行clock_opt命令创建时钟树执行增量的逻辑和布局优化运行时钟树优化对时钟网络进行布线通过设置，clock_opt还能进行修复holdtime违规执行内部时钟平衡LogicalDataPhysicalDataplace_optclock_optroute_optAnalysis Outputclock_optclock_optRouting布线器进行:GlobalRouteTrackAssignmentDetailedRoute 然后执行大量的逻辑、布局、布线和串扰优化来产生最好的布线结果LogicalDataPhysicalDataplace_optclock_optroute_optAnalysis Outputroute_optroute_opt分析检查执行place_opt和route_opt命令后屏幕输出的设计总结:利用率WNS–WorstNegativeSlackTNS–TotalNegativeSlack单元放置的合法单元数量和面积设计规则违规用report_qor命令:每个路径组(clockgroup)WNS/TNS其它统计信息LogicalDataPhysicalDataplace_optclock_optroute_optAnalysis OutputAnalysisAnalysis–Details产生更加详细的报告显示所有违规路径终点report_constraint–all_violators详细显示建立时间最坏的那条路径report_timing报告物理设计统计信息(如.利用率)report_design-physical分析阻塞阻塞图(GUI)report_congestion采用一致性的名字Imperativewhenexportingdataalways!在Milkyway数据库中保存设计单元保存Verilog网表仅保存平面规划信息change_names–hierarchy–rulesverilogsave_mw_cel-asroutedwrite_def-outputfloorplan.defwrite_floorplanfloorplan.tclwrite -formatverilog\

-hierarchy-outputrouted.vOutputLogicalDataPhysicalDataplace_optclock_optroute_optAnalysis OutputOutputExample“run”Scriptlappendsearch_path./design_data../db../tlupsetlink_library"*gates.dbrams.db"settarget_library"gates.db"create_mw_libmy_lib.mw\–technologytech_file.tf\–mw_reference_library"mwlib/gatesmw_lib/rams“\-openimport_designsmy_design.v\ -formatverilog\ -topMYDESIGNset_tlu_plus_files\ -max_tluplusabc_max.tlup\ -min_tluplusabc_min.tlup\ -tech2itf_mapabc.map ;explainedlater…read_sdcmy_design.sdccheck_timingread_def-allow_physicalmy_design.defcheck_physical_constraintsplace_optclock_optroute_optsave_mw_cel-asroutedUNIX$icc_shell–frun.tcl|teemyrun.logrun.tclLocalDiskSpaceUsage在ICCompiler进行版图设计流程时,要求足够的磁盘空间去存储数据，例如:上面表显示通过每个步骤要求的磁盘空间增加，因此完成150K门的设计,需要56+62+120=238MB.

Designsize

Milkywaydatabase**size(instances)place_optclock_optroute_opt

150K

56MB

62MB

120MB250K

150MB

178MB

303MB400K

242MB

269MB

460MB625K

277MB

325MB

569MB700K

344MB

419MB

741MB850K

917MB

950MB

1.5GB

**thisincludesallCEL/ROUTE/PARA/...viewsplusanyCELattachments静态时序分析ICCompiler的静态时序分析设置与DesignCompiler、PrimeTime相同用ICCompiler进入分析前,需要对库和操作条件设置.如:setlink_library"*abcmax.db"set_operating_conditions\ –analysis_typeon_chip_variation\ -maxabc_wc-max_libraryabc_max

Usingoperatingconditions‘abc_wc'foundinlibrary‘abc_max'.report_timing–delaymax|minMoreComplexSetupinUnit4!时序优化设置在ICCompiler中，由许多变量和命令来控制时序优化.例如：setenable_recovery_removal_arcstruesettiming_self_loops_no_skewtrueset_cost_priority{max_delaymax_capacitance}set_ahfs_options-enable_port_punchingtrue记住所有这些变量和命令是很麻烦–用GUI提供帮助!用GUI执行时序优化设置,然后把这些变量和命令拷到设置文件中时序优化设置(2/2)基于单元和网络计算时序延时ICC为每个单元和网络计算延时为计算延时，ICC需要知道每个网络的寄生RCCellDelay=

(InputTransitionTime,Cnet+Cpin)NetDelay=

(Rnet,Cnet+Cpin)0.5nsCnetCpinRnetTLU+模型

ICCompiler用网络的几何形状和TLU+查找表来计算CandR超深亚微米加工的效应模型SingleProcessFile

(ITF)TLU+ICC,PC,Astro™nxtgrdStar-RCXT™超深亚微米加工效应ConformalDielectricMetalFillShallowTrenchIsolationCopperDishing:DensityAnalysisWidth/SpacingTrapezoidConductorSeeAppendixBfordetailsGeneratingTLU+ModelsITF(加工文件)由Foundry厂提供TLU+模型通常是不提供从ITF产生TLU+Where: -itf2TLUPlus generatesTLU+insteadofnxtgrdfile

-i istheITFfile

-o istheoutput,binaryTLU+modelfileunix%grdgenxo-itf2TLUPlus-i<ITFfile>-o<TLU+file>AlwaysusethelatestStar-RCXTreleasetogeneratethemodels.set_tlu_plus_files\ -max_tluplusabc_max.tlup\ -min_tluplusabc_min.tlup\ -tech2itf_mapabc.mapLoadingTLU+ModelsICCompiler检查search_path去查找TLU+files对TLU+设置执行一致性检查确保正确的TLU+和map文件check_tlu_plus_files映射文件映射文件从.tf(MW技术文件)层/过孔名映射到Star-RCXT，.itf层/过孔名。Layer"METAL"{layerNumber =14maskName ="metal1"

…DIELECTRICcm_extra3{THICKNESS=0.06ER=4.2}CONDUCTORcm{THICKNESS=0.26WMIN=0.16…}DIELECTRICdiel1d{THICKNESS=0.435ER=4.2}…abc.itfabc.tfconducting_layers

poly poly

metal1 cm

metal2 cm2

…abc.map计算单元和网络延时从TLU+模型中可知道网络的寄生RC，则可计算延时对于单元延时，只需要Ctotal/Ceff计算算法计算网络延时有：Elmore,ArnoldiC1R1R2R3C3C4U2U1C2预布线时的延时计算算法布局后布线前，基于虚拟布线来估计线长度由于虚拟布线只是一种估算，用Elmore模型进行延时计算Pin-to-pintimingVirtualRoute布线后的延时计算算法布线后，具体线网已经明确，因此抽取更加精确默认情况下仍用Elmore模型在后布线计算时可打开Arnoldi

模型DetailedRouteBasicFlowSummaryYoushouldnowbeableto:CreateaMilkywaylibrarytoholdyourdesignReadallnecessaryfilesrequiredtorun

ICCompiler,resolvingcommonerrors/warningsSetuptimingforanalysisandoptimizationsExecutethebasicflowforplacement,CTSandroutinginICCompiler45minutesLab1:BaselineflowforICCompilerGoals:SetupdesigndatabaseandtimingPerformbaselineplace,cts&routeoperationswithassociateddefaultoptimizationsCreateMWdatabasewithattachedlibrariesplace_optclock_optroute_optAnalysisandOutputReaddesign,constraints,floorplan设置设计资料库课时间在默认的优化下执行基本操作流程：布局、时钟树综合和布线操作。AppendixAMW参考库的准备MigrationfromDB/PDBtoMW:TerminologyDC/PCTerminologyMilkywayTerminologyLibraryCompiler(compilelibrary)

read_lib,write_libMilkywaytool(create/edit

MilkywayLibrary)read_lef,read_plib,…Database(db)Librarydb(timing)

PDB(physical)

Designdb/ddcMilkywayLibraryLibrarydb(canbepartof

RefLibasLMview)

ReferenceLibrary

DesignLibrarySetupwithoutusingMilkyway:search_path

link_library

target_librarySetupusingMilkywaylibrary:se