计算机系统结构课件

计算机中系统结构AbstractionAbstractionistheartofgeneralizingaconceptorideafromaspecificinstanceLookatsamethingfromdifferentperspective,ignoreinternaldetailsAbstractioninComputerHardwareTransistor→Gate→SimpleCircuit→

ComplexCircuit→ComponentInthischapterwewillbestudyingthecomponentsthatmakeupacomputerTopdownviewofacomputerCOMPUTERARCHITECTURETherearemanydifferentcomputers: Multi-milliondollarsupercomputers Milliondollarmainframes Minicomputers Workstations Laptops Lessthan$100handheldpersonaldigitalassistantsAlthoughthepricetagsontheseandthespeed,capacity,andsoftwarediffersignificantly,theyMOSTarebasicallydesignedthesame.VONNEUMANNARCHITECTUREThereare3majorunitsinacomputertiedtogetherbybuses:1)Memory

Theunitthatstoresandretrievesinstructionsanddata.2)Processor:Theunitthathousestwoseparatecomponents:Thecontrolunit:Repeatsthefollowing3tasksrepeatedly Fetchesaninstructionfrommemory Decodestheinstruction ExecutestheinstructionThearithmetic/logicunit(ALU):Performsmathematicalandlogicaloperations.3)Input/Output(I/O)Units:Handlescommunicationwiththeoutsideworld.VonNeumannArchitecture Thearchitectureisnamedafterthemathematician,JohnVonNeumann,whosupposedlyproposedstoringinstructionsinthememoryofacomputerandusingacontrolunittohandlethefetch-decode-executecycle: fetchaninstruction decodetheinstruction executetheinstructionInterestingly,asimilararchitecturewasproposedin1830byCharlesBabbageforhisAnalyticEngine:ALU millmemory storecontrolunit operator(processcardsstoringinstructions)I/Ounits output(typewriter)PortionofthemilloftheAnalyticalEnginewithprintingmechanism,underconstructionatthetimeofBabbage’sdeath.©ScienceMuseum/Science&SocietyPictureLibraryProcessorPictorialViewof

ComputerOrganizationMemoryControlUnitALUInput/OutputFlowofInformationThepartsareconnectedtooneanotherbyacollectionofwirescalledabusFigure

5.2DataflowthroughavonNeumannarchitectureProcessorTHEUNITSOFACOMPUTER

(Notethis

MODIFIESFigure5.18onpage220TheLabSimulatorAfterLoadingaProgramRAMandROMRAMstandsforRandomAccessMemoryInherentintheideaofbeingabletoaccesseachlocationistheabilitytochangethecontentsofeachlocationROMstandsforReadOnlyMemoryThecontentsinlocationsinROMcannotbechangedRAMisvolatile,ROMisnotThismeansthatRAMdoesnotretainitsbitconfigurationwhenthepoweristurnedoff,

butROMdoesMEMORYUNIT

(orRAM-RandomAccessMemory)Eachcellhasanaddress,startingat0andincreasingby1foreachcell.Acellwithalowaddressisjustasaccessibleasonewithahighaddress-hencethenameRAM.Thewidthofthecelldetermineshowmanybitscanbereadorwritteninonemachineoperation&isnormallyapower2AcellistypicallyabytetodayMemoryMemoryisacollectionofcells,

eachwithauniquephysicaladdressThesizeofacellisnormallyapowerof2,typicallyabytetoday.MemoryAcellisthesmallestaddressableunitofmemory–i.e.onecellcanbereadfrommemoryoronecellcanbewrittenintomemory,butnothingsmaller.WhatisaRegister?Datacanbemovedintoandoutofregistersfasterthanfrommemory.Ifwecouldreplaceallofmemorywithregisters,wecouldproduceavery,veryfastcomputer...But,thepricewouldbeterriblyprohibitive.Mostcomputershavequiteafewregistersthatservedifferentpurposes.We’llseehowtheMARandtheMDRareused.AnotherTypeofMemory:CacheCachespeedisfasterthanmainmemoryandslowerthanregisters.Ourlabsimulatorwillnotuseanycachememory,butcomputerstodaydouseit.Tospeedupretrievalsfrommemory,itemsareprefetchedintocachememoryandthen,whenneededbytheCPU,theyareretrievedfromcachememoryratherthanmemory.However,tokeepthingssimple,we’llassumefetcheswilloccurfrommainmemory.THEUNITSOFACOMPUTERMEMORY: Storesandretrievesinstructionsanddata. WesawinChapter4thatnumbersandcharacters(thedata)canberepresentedinbinaryformats. Instructionsarealsorepresentedinbinaryform:Differentcomputersusedifferentinstructionsetsandformats.Wewilluseaverysimple,genericformatforwhatiscalleda1-address

machine:addressof12bitsopcodeof4bitsOthermachinesuse2-address,3-address,andmixedformatinstructions.A2-addressmemorywillbediscussedlater.OPCODES(i.e.1-AddressOperationCodes)

REF:221,Fig5.19ArithmeticOpCodes0000load0001store0010clear0011add0100increment0101subtract0110decrementI/0OpCodes1101in1110outLogic/ControlOpCodes0111compare1000jump1001jumpgt1010jumpeq1011jumplt1100jumpneq1111haltWewillseehowtheseareusedlater.STRUCTUREOFRANDOMACCESSORMAINMEMORYMemory1bitaddresses:

012•••2N-1

•••MAR-NbitsonememorycellWbitswideMemoryAddressRegisterMemoryDataRegisterMDR-kWbitsALLACOMPUTERDOESIS...Repeatforever(oruntilyoupulltheplugorthesystemcrashes)1)FETCH2)DECODE3)EXECUTESOMESIZESDICTATEDBYTHESTRUCTUREOFMAINMEMORYWithourinstructionhavingtheformof 4bitsfortheopcode 12bitsfortheaddressifweplantohaveoneinstructionpermemorycell,thenweneedtohaveforourcomputerAnMAR(memoryaddressregister)of12bits.Amemorysizeofatmost212=22*210=4KAmemorywidthof4+12=16bitsIfMDR(memorydataregister)is16bits,thenthelargestsizednumberis 01111111111111112=215-1=32,768.OTHERCOMPONENTSOFTHEMEMORYUNITBesidestheRandomAccessMemoryandtheMARandMDR,twoothercomponentsexist:1)Fetch/storecontroller:SendsasignaltoFetchorStore2)Memorydecodercircuits:(Ref,Chpt4,pg180-182)ANx2NdecoderhasNinputlinesand2Noutputlines.WhentheNinputlinesaresetto0sor1sandtheNvaluesareinterpretedasabinarynumber,theyrepresentallthenumbersbetween0and2N-1.Theoutputtothedecoderisa1onthelineidentifiedbythevalueoftheinputanda0onalltheotherlines.Example:011

0112=3sothelinelabeled3,the4thfromthetopoutputsa1andallotherlinesoutputa0.3x8decoderAdecoderselectsonelineforapulse,whentheinputlinesareinterpretedasabinarynumber.Whyisthisusefulforamemoryunit?USINGTHEDECODERCIRCUITTOSELECTMEMORYLOCATIONS01234567•••154x24decoder10111MAR0000THEDECODERCIRCUITCANBEBUILTFROMAND-OR-NOTGATESSeeFigure4.29onpage181fora2x4decodercircuit.Aswithallcircuits,tobuildadecoder, 1)Buildatruthtableforthecircuit(Forexample,fora3x8decoder,thereare8rows,3inputchoices,and8outputvalues). 2)Usethesum-of-productsalgorithmtofindtheBooleanexpressionforthetruthtable. 3)Buildthecircuit.Thedecodercircuitdoesn'tscalewelli.e.asthenumberofbitsintheMARincreases,thenumberofoutputlinesforthedecodergoesupexponentially.MostcomputerstodayhaveanMARof32bits.Thus,ifthememorywaslaidoutasweshowedit,wewouldneeda32x232decoder!Note232is22230=4GSomostmemoryisnot1dimensional,but2-dimensional(oreven3-dimensionalifbankedmemoryisused).2-DMEMORY0111MAR2x4decoder2x4decodercolumnsrowsNotethata4x16

decoderwasusedforthe1-Dmemory.Howdoesthememoryunitwork?Tracethefollowingoperation:

StoredataDinmemorylocation0.DD00D0DsDHowdoesthememoryunitwork?Tracethefollowingoperation:1)FetchdataDfrommemorylocation1.2)ObtainaninstructionIfrommemorylocation7.Howdoesthecomputerdistinguishbetween1)and2)above?Weneedtolookatthecontrolunitlater.1DfDIHowDoestheControlUnitWork?ControlUnitAControlUnitistheunitthathandlesthecentralworkofthecomputer.TherearetworegistersinthecontrolunitTheinstructionregister(IR)containstheinstructionthatisbeingexecutedTheprogramcounter(PC)containstheaddressofthenextinstructiontobeexecutedTheALUandthecontrolunittogetherarecalledeithertheProcessorCentralProcessingUnit(i.e.,CPU)HowDoestheControlUnitWork?ThePCholdstheaddressofthenextinstructiontobeexecuted.Whateverisstoredatthataddressisassumedtobeaninstruction.Oncetheinstructionisfetched,thePCisincremented.THECONTROLUNITPC+1

0011|addressIRinstructiondecoderenableaddline3Tracewhathappensduring fetch decode executeNote:ThePCisincrementedaftereachfetch.THEARITHMETIC-LOGICUNIT

(ALU)Thetextshowsmultipleregisterswhichistypical.However,weareworkingwitha1-addressmachinewhichhasasinglesystemregisterR.OtherregistersareattachedtotheALU.THEARITHMETIC/LOGICUNITRAL1AL2ALUcircuitsmultiplexorselectorlinesoutput(Inthelabyouwillseewherethiswillgo)Whatisamultiplexorandhowdoesitwork?GTEQLTconditioncoderegisterRegisterROtherregistersMULTIPLEXORCIRCUITmultiplexorcircuit2Ninputlines0122N-1NselectorlinesoutputInterprettheselectorlinesasabinarynumberA.TheoutputisthevalueonthelinenumberedAExample:multiplexorwithN=201Note:Amultiplexorisaswitch.ItshouldbeobviousthatamultiplexorcanbebuiltwithAND-OR-NOTgates.(seepage179)THECONDITIONCODEREGISTER

partoftheALUWhenevera COMPAREXcommandisexecuted,aconditioncode(whichisasinglebit)isset(toa1).ThesecodesareusedtocontrolJUMPcommands.GTissetifCON(X)>REQissetifCON(X)=RLTissetifCON(X)<RWhathappenswiththesequence: LOAD1 COMPARE2 JUMPGT51)ifaddress1holds15andaddress2holds12?2)ifaddress1holds12andaddress2holds15?ADDX

XDDADDXfALU1&ALU2EE+DEDE+DE+DLAST,BUTNOTLEAST,THEI/ODEVICESPictorially,theselookthesimplest,butinreality,theyformthemostdiversepartofacomputer.Includes:keyboards,monitors,joysticks,mice,tablets,lightpens,spaceballs,Input/OutputUnitsAninputunitisadevicethroughwhichdataandprogramsfromtheoutsideworldareenteredintothecomputerKeyboard,themouse,andscanningdevicesAnoutputunitisadevicethroughwhichresultsstoredinthecomputermemoryaremadeavailabletotheoutsideworldPrintersandvideodisplayterminalsI/OUNITSProcessorMemoryI/ObufferControl-logicI/0deviceEachdeviceisdifferent,butmostareinterruptdriven.ThismeanswhentheI/Odevicewantsattention,itsendsasignal(theinterrupt)totheCPU.NOWUSETHECOMPLETEARCHITECTURETOTRACETHEACTIONSTAKENFOREXECUTING

INXOUTXLOADXSTOREXINCREMENTXWealreadyhavedone:ADDXCOMPAREXJUMPXJUMPLTXINX

XDINXsDDOUTX

XDDOUTXfDLOADX

LOADXXDfDDSTOREX-youshouldbeabletodothisnowINCREMENTX

INCRXXDD+1COMPAREX

COMPXaswithotheropsfetchDDDSettheseaccordingtocompopJUMPX

JUMPXXJUMPLTX

IfLT=1,moveXtoPCTheJumpCommands

Allowustoconstructbranchesandloopsaswewillsee.TheirpurposeistochangethePC–programcounterJUMPX–alwayschangePCtoaddressXJUMPGTX–changePCtoaddressXifandonlyifGT=1JUMPEQX-changePCtoaddressXifandonlyifEQ=1JUMPLTX-changePCtoaddressXifandonlyifLT=1JUMPNEQX-changePCtoaddressXifandonlyifEQ=0SecondaryStorageDevicesBecausemostofmainmemoryisvolatileandlimited,itisessentialthattherebeothertypesofstoragedeviceswhereprogramsanddatacanbestoredwhentheyarenolongerbeingprocessedSecondarystoragedevicescanbeinstalledwithinthecomputerboxatthefactoryoraddedlaterasneededMagneticTapeThefirsttrulymassauxiliarystoragedevicewasthemagnetictapedriveAmagnetictapeCompactDisksACDdriveusesalasertoreadinformationstoredopticallyonaplasticdiskCD-ROMisRead-OnlyMemoryDVDstandsforDigitalVersatileDiskAreAllArchitecturesthevonNeumannArchitecture?No.OneofthebottlenecksinthevonNeumanArchitectureisthefetch-decode-executecycle.Withonlyoneprocessor,thatcycleisdifficulttospeedup.I/Ohasbeendoneinparallelformanyyears.WhyhaveaCPUwaitforthetransferofdatabetweenthememoryandtheI/Odevices?Mostcomputerstodayalsomultitask–theymakeitappearthatmultipletasksarebeingperformedinparallel(wheninrealitytheyaren’taswe’llseewhenwelookatoperatingsystems).But,somecomputersdoallowmultipleprocessors.SynchronousprocessingOneapproachtoparallelismistohavemultipleprocessorsapplythesameprogramtomultipledatasetsFigure5.6ProcessorsinasynchronouscomputingenvironmentPipeliningArrangesprocessorsintandem,whereeachprocessorcontributesoneparttoanoverallcomputationFigure5.7ProcessorsinapipelineShared-MemorySharedMemoryProcessorProcessorProcessorProcessorLocalMemory1LocalMemory2LocalMemory3LocalMemory4Differentprocessorsdodifferentthingstodifferentdata.Ashared-memoryareaisusedforcommunication.ComparingVariousTypesofArchitecture

Typically,synchronouscomputershavefairlysimpleprocessorssotherecanbemanyofthem–inthethousands.OnehasbeenbuiltbyParacel(GeneMatcher)withover1Mprocessors.UsedbyCeleraincompletingthedescriptionofthehumangenomesequencingPipelinedcomputersareoftenusedforhighspeedarithmeticcalculationsasthesepipelineeasily.Shared-memorycomputersbasicallyconfigureindependentcomputerst