Ansys2025全球仿真大会：全面的2.5D IC设计电源完整性分析

ComprehensivePowerIntegrityAnalysis

of

2.5DIC

Design丁萍/中兴微电子©2025ANSYS,Inc.Motivation©2025ANSYS,Inc.

Motivation

Supercomplex2.5DIC

design•

SoCdies,memory,

siliconbridges

sharemultiplepower/grounddomains,operating

frequency/scenarios

arevery

complex•Interposersizecanachieve

thousands

of

square

millimeters•Totalpowerconsumptioninthekilowatt

class•Overallsizeof

powerdeliverynetwork(PDN)

can

exceedhundreds

of

BillionNodes/Resistors!

Powersharedbetweenmultiple

SoCdies,memories,RDL,

silicon

bridges

andpackage•Powernoisecanpropagateacrossall

these

components•RapidlychangingworkloadsrequirethePDNtobeabletorespond

quickly

andmaintain

voltage

stability

Cost-effectiveness

management•

Superlargepowergridlayoutrequiresincreasedroutingresources•Cannolongerreserveamargin

like

the

traditional

way

Needapreciseapproachtopredict/analyzethe

entire2.5DIC

PDN

quality

and

accurately

capture

coupling

effectsbetween

each

component

atbothprototypingandsign-offstageLogicDie2LogicDie

1PackageLogicDie

1Package

一ubump▲

RDLInterposer

C4bumpBGAballSiTSVPackage

一

ubump▲

SiliconInterposer

BGAball

BGAballLogicDie

1LogicDie2LogicDie2MetalLayersSiliconTSVC4bumpTIVC4bumpubumpRDL3

Motivation•Critical

decisionsontopologyandplacement

areneedto

be

made

at

an

early

stage•

Requiresfast,yetaccurate,trade-offstudiesforpowerintegrity•

Early-stagetosign-off

full-pathpowerintegritymonitor•

Analysismust

accountfordifferences

in:•

Aspectratioof

features,finefeaturesvs

gross

features

in

same

model•Silicon~1um,PKG(

10s/100s

ums)

,BRD

(

mm

)•

~10k

connection->Millions

connections•Concatenationofdisparatedatabases•

Mustsupportvariety

of

dataformats•Mustbefast,efficient,

and

scalable•

Mustbeabletofilteroutthenecessarycontext

forthe

specific

assessment,

e.g.

Siliconmetal

layersof

focus,bumps,RDL,TSV,TIV,portsand

specificpower

delivery•

Protectionof

IP,encryptionof

Inputs/Outputs4MainIdea©2025ANSYS,Inc.EngineeringGoals

Drivecriticalphysicalimplementationdecisionsforpowerefficiencyatprototypingstage,achievebestPPAC(Performance-Power-Area-Cost)

Optimizemostappropriatepowerdesignstrategies,suchasdecouplingcapacitor/TSV/TIVconfigurationstrategyandpower/groundplanes,etc.

OptimizeDeepTrenchCapacitor(DTC)configurationandplacementonsiliconbridgestoensurea

stablepowersupplyenvironment

Fast,efficient,andscalablePDNanalysisapproachtoanalysistheentiresuper

complex

2.5DIC

systemChip-centricfull2.5DICsystemPIcheck,

concurrent

simulationtakes

into

accounttheimpact

from

sharedP/GnetsandDTCinsiliconbridge,

and

detailed

die2diecouplingeffectsSystem-centric

full2.5DICsystemPIcheck,

accurate

CPM(chippowermodel)

basedsystem

analysisLeverage

rollupor

ROM(ReducedOrderModel)

technology

forfaster

TAT&

lowermemory

footprint■

ForeachSoCdie,enableBQM(BuildQualityMetric)checkwithpreliminarycollateral,

findsweaknessissues

in

entirepowergrid,

evenbeforeinstance

placements EnableinterposerPDNqualityearlycheck,

detectsweakness

in

grid

density,TSV/TIVplacement,DTCconfiguration

andpower/groundplanes

MainIdeaEarly-stage

Signoff-stagePDN

Check

PDNValidationBQM:current

assignmentinside

SoCdiesInterposerPDNearly

check6Results©2025ANSYS,Inc. InterposerStatic/DynamicIR

AnalysisatEarlyStage

InterposerPDNanalysiswithpreliminary

collateral,currentvalueorwaveform

canbe

assigned

on

eachubump

to

check

Interposer

IR/EMatprototyping

stage

Static/dynamic

IR/EMhotspotheatmaphelptocheckpowergriddensity,bumpplacement,

connectionpointplacements

and

DTC

contributionat

early

stage

ByincreasingtheDTCcapacitancefrom50nF

to

100nF

and

optimizing

the

placement

of

the

DTCs

(placing

them

as

close

as

possible

totheloadside),7%reductionin

dynamic

voltage

drop

canbe

seen

close

to

the

load

sideQuicklydetectif

interposer/siliconbridgemeetsthedynamicPI

spec

atbumps/TSV/TIV,

etc.AllowSoCdiesandinterposertoiterate

theirPDN

separately,streamliningandacceleratingearlycross-design

team

deliveryProvidesguidanceforSoCdies

on

dynamic

bump

fluctuationEvaluateproperDTCcapacitorplacementandquantityat

an

early

stageVDD2

node

dropheatmap

Before

DTC

OptimizationVDD2node

dropheatmap

After

DTC

OptimizationDynamicIRheatmapBeforeVS.

AfterDTCOptimizationPDN,VDD2idealvoltage:

0.4VBeforeDTCopt:worstdrop32mVAfterDTCopt:worstdrop4mVPGweaknessdetected

atearly

stage~500+APbumps

disconnectedduetoRVmissingPDNSystemResponseAPRRule&Die

Area

SpecVSSweakconnectionduetomissingVIA1AverageBumpVoltageCDTC

&

Cdie

RDL1weakconnection

early

Optimal

WorstIRdropdiff:

7%RDL8DataInputsSoCdata:DEF/LEF,APL,

LIB,

SPEFetc.

CP(µBump)

:LocationfileandparasiticsInterposerdata:DEF/LEF.LIB,

SPEFetc.C4Bump:Locationfileandparasitics

Multi

SoCdies,memories,RDL,siliconbridges

andpackage

are

analyzed

simultaneously

withbig

data

EDA

tool

Analysisusethemodel

accordingly•AllchipletsuseDEF•MasterchipletsuseDEF,clonedchiplets

usereduced

model

Leveragevectoredorvectorlessactivitiesinformationto

ensureworst

casepower

consumption

analyses

Enablecurrentdensity-basedDCEM&RMS

EM

checking

onthe

entire

2.5DIC

design

Siloeddesigngroupshaveacommonworkflow:

offchip<->

onchip Multi-dieLargePDNPower

Analysisat

Sign-off

Stage

LEF/DEF

/

RedHawk-SCLEF/DEFLEF/DEF/interpos

erRDL/silicionInterposerbridgewith9•Aidsinearlyidentificationof

risksanddeficienciesin

package,

help

packagedesign

optimization

withminimizeeffort•Through

static

SoC

bump

current-aware

&

package

aware

DC

IR

simulation

ofinterposer,

large

resistanceissueduetoweakconnectionof

theVDDnetonthepackageisdetected•Through

dynamic

SoCbump

current-aware

&

package

aware

transient

hotspot

simulation

ofinterposer,highdynamicvoltagedropobservedonthe

interposer

ledto

the

discovery

of

a

localized

large

inductance

problemcausedbyroutingcongestionandfragmentedroutingonthepackage Package-awareInterposerPDNcheckIRdrop:VDD1:

11.3uVVDD2:8.3mVVSS:3.4mVWorseStatic

IRIRdrop:VDD1:42.6uVVDD2:

10mVVSS:4.3mVIRdrop:VDD1:0.6mVVDD2:25.5mVVSS:28mVWorseDynamic

IRIRdrop:VDD1:

142mVVDD2:

183mVVSS:525mVdifferent

currentsatbump(of

differentRCvalues

and

scenarios)differnerntIR

drop

atbumpDynamic

run

w/opkg

Dynamic

run

w/pkgdemo

caseresultsStatic

run

w/opkg

Static

run

w/pkgPower

Spec10Summary©2025ANSYS,Inc.

Summary

Itisimportanttoperformpowerintegrity

simulation

attheearly

design

stage

to

establish

the

decoupling

capacitor

configurationstrategyforchip/interposer/packagelevel,themulti-layerpowerand

groundplanes,

andtopredictpotentialproblems

and

adju