计算机组成原理教学课件：5-Large-and-Fast-Exploiting-Memory-Hi

Computer

Organization&Design

—TheHardware/SoftwareInterface2026/4/201PresentationOutlineRandomAccessMemoryanditsStructureMemoryHierarchyandtheneedforCacheMemoryTheBasicsofCachesCachePerformanceandMemoryStallCyclesImprovingCachePerformanceMultilevelCachesLargearraysofstoragecellsVolatilememoryHoldthestoreddataaslongasitispoweredonRandomAccessAccesstimeispracticallythesametoanydataonaRAMchipOutputEnable(OE)controlsignalSpecifiesreadoperationWriteEnable(WE)controlsignalSpecifieswriteoperation2n×mRAMchip:n-bitaddressandm-bitdataRandomAccessMemoryRAMAddressDataOEWEnmMemoryTechnologyStaticRAM(SRAM)forCacheRequires6transistorsperbitRequireslowpowertoretainbitDynamicRAM(DRAM)forMainMemoryOnetransistor+capacitorperbitMustbere-writtenafterbeingreadMustalsobeperiodicallyrefreshedEachrowcanberefreshedsimultaneouslyAddresslinesaremultiplexedUpperhalfofaddress:RowAccessStrobe(RAS)Lowerhalfofaddress:ColumnAccessStrobe(CAS)StaticRAMStorageCellStaticRAM(SRAM):fastbutexpensiveRAM6-TransistorcellTypicallyusedforcachesProvidesfastaccesstimeCellImplementation:Cross-coupledinvertersstorebitTwopasstransistorsRowdecoderselectsthewordlinePasstransistorsenablethecelltobereadandwrittenTypicalSRAMcellVccWordlinebitbitDynamicRAMStorageCellDynamicRAM(DRAM):slow,cheap,anddensememoryTypicalchoiceformainmemoryCellImplementation:1-Transistorcell(passtransistor)Trenchcapacitor(storesbit)BitisstoredasachargeoncapacitorMustberefreshedperiodicallyBecauseofleakageofchargefromtinycapacitorRefreshingforallmemoryrowsReadingeachrowandwritingitbacktorestorethechargeTypicalDRAMcellWordlinebitCapacitorPassTransistorTypicalDRAMPackaging24-pindualin-linepackagefor16Mbit=222

4memory22-bitaddressisdividedinto11-bitrowaddress11-bitcolumnaddressInterleavedonsameaddresslines

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24

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A4

A5

A6

A7

A8

A9

D3

D4

CAS

OE

Vss

Vss

A0

A1

A2

A3

A10

D1

D2

RAS

WE

Vcc

Vcc

NC

LegendAiCASDjNCOERASWEAddressbiti

ColumnaddressstrobeDatabitj

NoconnectionOutputenableRowaddressstrobeWriteenableTypicalMemoryStructureRowaddresslatchr...2r×2c

×mbitsCellMatrixRowDecoderSense/writeamplifiersColumnDecoder...Coladdresslatchc=n–rDataRowLatch2c×mbitsmDRAMOperationRowAccess(RAS)LatchanddecoderowaddresstoenableaddressedrowSmallchangeinvoltagedetectedbysenseamplifiersLatchwholerowofbitsSenseamplifiersdrivebitlinestorechargestoragecellsColumnAccess(CAS)readandwriteoperationLatchanddecodecolumnaddresstoselectmbitsm=4,8,16,or32bitsdependingonDRAMpackageOnread,sendlatchedbitsouttochippinsOnwrite,chargestoragecellstorequiredvalueCanperformmultiplecolumnaccessestosamerow(burstmode)BurstModeOperationTrendsinDRAMYearProducedChipsizeTypeRowaccessColumnaccessCycleTimeNewRequest198064 KbitDRAM170ns75ns250ns1983256 KbitDRAM150ns50ns220ns19861 MbitDRAM120ns25ns190ns19894 MbitDRAM100ns20ns165ns199216 MbitDRAM80ns15ns120ns199664 MbitSDRAM70ns12ns110ns1998128 MbitSDRAM70ns10ns100ns2000256 MbitDDR165ns7ns90ns2002512 MbitDDR160ns5ns80ns20041 GbitDDR255ns5ns70ns2006 2GbitDDR250ns3ns60ns20104GbitDDR335ns1ns37ns20128GbitDDR330ns0.5ns31nsSDRAMandDDRSDRAMSDRAMisSynchronousDynamicRAMAddedclocktoDRAMinterfaceSDRAMissynchronouswiththesystemclockOlderDRAMtechnologieswereasynchronousAssystembusclockimproved,SDRAMdeliveredhigherperformancethanasynchronousDRAMDDRisDoubleDataRateSDRAMLikeSDRAM,DDRissynchronouswiththesystemclock,butthedifferenceisthatDDRreadsdataonboththerisingandfallingedgesoftheclocksignalTransferRates&PeakBandwidthStandardNameMemoryBusClockMillionsTransferspersecondModuleNamePeakBandwidthDDR-200100MHz200MT/sPC-16001600MB/sDDR-333167MHz333MT/sPC-27002667MB/sDDR-400200MHz400MT/sPC-32003200MB/sDDR2-667333MHz667MT/sPC-53005333MB/sDDR2-800400MHz800MT/sPC-64006400MB/sDDR2-1066533MHz1066MT/sPC-85008533MB/sDDR3-1066533MHz1066MT/sPC-85008533MB/sDDR3-1333667MHz1333MT/sPC-1060010667MB/sDDR3-1600800MHz1600MT/sPC-1280012800MB/sDDR4-32001600MHz3200MT/sPC-2560025600MB/s1Transfer=64bits=8bytesofdataDRAMRefreshCyclesTime

Threshold

voltage

0Stored

1Written

Refreshed

Refreshed

Refreshed

RefreshCycle

Voltage

for1

Voltage

for0

RefreshcycleisabouttensofmillisecondsRefreshingisdonefortheentirememoryEachrowisreadandwrittenbacktorestorethechargeSomeofthememorybandwidthislosttorefreshcyclesLossofBandwidthtoRefreshCyclesExample:A256MbDRAMchipOrganizedinternallyasa16K

16KcellmatrixRowsmustberefreshedatleastonceevery50msRefreshingarowtakes100nsWhatfractionofthememorybandwidthislosttorefreshcycles?Solution:Refreshingall16Krowstakes:16

1024

100ns=1.64msLossof1.64msevery50msFractionoflostmemorybandwidth=1.64/50=3.3%ExpandingtheDataBusWidthOEWEAddressDataOEWEAddressDataOEWEAddressData...Datawidth=m×pbits..mmNext...RandomAccessMemoryanditsStructureMemoryHierarchyandtheneedforCacheMemoryTheBasicsofCachesCachePerformanceandMemoryStallCyclesImprovingCachePerformanceMultilevelCachesProcessor-MemoryPerformanceGap1980–Nocacheinmicroprocessor1995–Two-levelcacheonmicroprocessorCPUPerformance:55%peryear,slowingdownafter2004PerformanceGapDRAM:7%peryearTheNeedforCacheMemoryTypicalMemoryHierarchyRegistersareatthetopofthehierarchyTypicalsize<1KBAccesstime<0.5nsLevel1Cache(8–64KB)Accesstime:1nsL2Cache(512KB–8MB)Accesstime:3–10nsMainMemory(4–16GB)Accesstime:50–100nsDiskStorage(>200GB)Accesstime:5–10msMicroprocessorRegistersL1CacheL2CacheMainMemoryMagneticorFlashDiskMemoryBusI/OBusFasterBiggerPrincipleofLocalityofReferenceProgramsaccesssmallportionoftheiraddressspaceAtanytime,onlyasmallsetofinstructions&dataisneededTemporalLocality(intime)Ifanitemisaccessed,probablyitwillbeaccessedagainsoonSameloopinstructionsarefetchedeachiterationSameproceduremaybecalledandexecutedmanytimesSpatialLocality(inspace)Tendencytoaccesscontiguousinstructions/datainmemorySequentialexecutionofInstructionsTraversingarrayselementbyelementWhatisaCacheMemory?CacheanalogyStudyingbooksinlibraryOption1:Everytimeyouswitchtoanotherbook,returncurrentbooktoshelfandgetnewbookfromshelfLatency=5minutes.Option2:Keep10commonly-usedbooksonshelfabovedeskLatency=1minute.Option3:KeepthreebooksopentoappropriatelocationsondeskLatency=10seconds.CacheMemoriesintheDatapathALUresult3201D-CacheAddressData_inData_out32ALUoutDRd3WBDataRd432ALU32ABRd2clk5Rs5RdRt32RegisterFileRARBBusABusBRWBusW01E02310231I-CacheAddressPCInstructionInstructionImm16InterfacetoL2CacheorMainMemoryI-CachemissD-CachemissInstructionBlockDataBlockBlockAddressBlockAddressImm10AlmostEverythingisaCache!Incomputerarchitecture,almosteverythingisacache!Registers:acacheonvariables–softwaremanagedFirst-levelcache:acacheonL2cacheormemorySecond-levelcache:acacheonmemoryMemory:acacheonharddiskStoresrecentprogramsandtheirdataHarddiskcanbeviewedasanextensiontomainmemoryBranchtargetandpredictionbufferCacheonbranchtarget

andpredictioninformationMainmemoryisimplementedfromDRAMdynamicrandomaccessmemorycachesuseSRAMstaticrandomaccessmemorymagneticdiskFlashmemoryisusedinsteadofdisksinmanyembeddeddevices;2026/4/2026MemoryhierarchyUseasmallarrayofSRAM.Smallsofastandcheap.UsealargeramountofDRAM.CheaperthanSRAM,fasterthanflash/disk.Usealotofflashand/ordisk.Non-volatile.Cheap.Big.Don’ttrytobuy264bytesofanything.Use“virtualmemory”tomakeitlookliketheentireaddressrangeisavailable.AfewTBisenoughformostdesktopmachinestoday,orasmartphoneinafewyears.MemoryhierarchyUseasmallarrayofSRAM.FortheCACHE

(hopefullycoversmostloadsandstores).UseabiggeramountofDRAM.FortheMainmemory.UseaalotofDisk.ForVirtualmemoryandnonvolatilestorage.MemoryhierarchyCache(SRAM)Mainmemory(DRAM)Disk(magneticorfloatinggate)CostLatencyAccesstimeNext...RandomAccessMemoryanditsStructureMemoryHierarchyandtheneedforCacheMemoryTheBasicsofCachesCachePerformanceandMemoryStallCyclesImprovingCachePerformanceMultilevelCachesAVerySimpleMemorySystem741101201301401501601701801902002102202302402500123456789101112131415LdR1M[1]LdR2M[5]LdR3M[1]LdR3M[7]LdR2M[7]CacheProcessortagdataR0R1R2R3Memory2cachelines4bittagfield1byteblockVV31AVerySimpleMemorySystem741101201301401501601701801902002102202302402500123456789101112131415LdR1M[1]LdR2M[5]LdR3M[1]LdR3M[7]LdR2M[7]CacheProcessortagdataR0R1R2R3MemoryIsitinthecache?NovalidtagsThisisaCachemissAllocate:address

tagMem[1]block111000

132AVerySimpleMemorySystem1001101201301401501601701801902002102202302402500123456789101112131415LdR1M[1]LdR2M[5]LdR3M[1]LdR3M[7]LdR2M[7]CacheProcessor1tagdataR0R1R2R3Memory110lruMisses:1Hits:

01107410

33AVerySimpleMemorySystem1001101201301401501601701801902002102202302402500123456789101112131415LdR1M[

1]LdR2M[5]LdR3M[1]LdR3M[7]LdR2M[7]CacheProcessor1tagdataR0R1R2R3Memory110Misses:1Hits:

0110lru74Checktags:51CacheMiss10

1150534AVerySimpleMemorySystem1001101201301401501601701801902002102202302402500123456789101112131415LdR1M[

1]LdR2M[5]LdR3M[1]LdR3M[7]LdR2M[7]CacheProcessor15tagdataR0R1R2R3Memory110150Misses:2Hits:

0110lru7415011

35AVerySimpleMemorySystem1001101201301401501601701801902002102202302402500123456789101112131415LdR1M[

1]LdR2M[5]LdR3M[1]LdR3M[7]LdR2M[7]CacheProcessor15tagdataR0R1R2R3Memory110150Misses:2Hits:

0110150lru74Checktags:15,but1=1(HIT!)11

36AVerySimpleMemorySystem1001101201301401501601701801902002102202302402500123456789101112131415LdR1M[

1]LdR2M[5]LdR3M[1]LdR3M[7]LdR2M[7]CacheProcessor15tagdataR0R1R2R3Memory110150Misses:2Hits:

1110150lru7411011

37AVerySimpleMemorySystem1001101201301401501601701801902002102202302402500123456789101112131415LdR1M[

1]LdR2M[5]LdR3M[1]LdR3M[7]LdR2M[7]CacheProcessor15tagdataR0R1R2R3Memory110150Misses:2Hits:

1110150lru7411011

38AVerySimpleMemorySystem1001101201301401501601701801902002102202302402500123456789101112131415LdR1M[

1]LdR2M[5]LdR3M[1]LdR3M[7]LdR2M[7]CacheProcessor15tagdataR0R1R2R3Memory110150Misses:2Hits:

1110150lru7411075and71

(MISS!)17017011

739EECS370:IntroductiontoComputerOrganizationAVerySimpleMemorySystem1001101201301401501601701801902002102202302402500123456789101112131415LdR1M[

1]LdR2M[5]LdR3M[1]LdR3M[7]LdR2M[7]CacheProcessor17tagdataR0R1R2R3Memory110170Misses:3Hits:

1110150170lru7411

40EECS370:IntroductiontoComputerOrganizationAVerySimpleMemorySystem1001101201301401501601701801902002102202302402500123456789101112131415LdR1M[

1]LdR2M[5]LdR3M[1]LdR3M[7]LdR2M[7]CacheProcessor17tagdataR0R1R2R3Memory110170Misses:3Hits:

1110150170lru7471and7=7(HIT!)17011

41EECS370:IntroductiontoComputerOrganizationAVerySimpleMemorySystem1001101201301401501601701801902002102202302402500123456789101112131415LdR1M[

1]LdR2M[5]LdR3M[1]LdR3M[7]LdR2M[7]CacheProcessor17tagdataR0R1R2R3Memory110170Misses:3Hits:

2110170170lru7411

42CSCE21243MemoryHierarchyEachlevelofthehierarchystoresasubsetofthelevelbelowitEachlevelcanonlycommunicatewiththelevelbelowitFornow,assume2-levelhierarchyCPU-cache-RAMcacheisusuallyon-chipSometimesthedataweneedisnotincachehitrateBlockorlinespatiallocalitymisspenaltytimerequiredtomovealinetothetopofthehierarchy(mayvary)CPUcachemainmemorycache的基本结构FourBasicQuestionsonCachesQ1:Wherecanablockbeplacedinacache?BlockplacementDirectMapped,SetAssociative,FullyAssociativeQ2:Howisablockfoundinacache?BlockidentificationBlockaddress,tag,indexQ3:Whichblockshouldbereplacedonamiss?BlockreplacementFIFO,Random,LRUQ4:Whathappensonawrite?WritestrategyWriteBackorWriteThrough(withWriteBuffer)BlockPlacement:DirectMappedBlock:unitofdatatransferbetweencacheandmemoryDirectMappedCache:Ablockcanbeplacedinexactlyonelocationinthecache0000010100111001011101110000000001000100001100100001010011000111010000100101010010110110001101011100111110000100011001010011101001010110110101111100011001110101101111100111011111011111Inthisexample:Cacheindex=leastsignificant3bitsofMemoryaddressCacheMainMemoryDirect-MappedCacheAmemoryaddressisdividedintoBlockaddress:identifiesblockinmemoryBlockoffset:toaccessbyteswithinablockAblockaddressisfurtherdividedintoIndex:usedfordirectcacheaccessTag:most-significantbitsofblockaddress Index=BlockAddress

mod

CacheBlocksTagmustbestoredalsoinsidecacheForblockidentificationAvalidbitisalsorequiredtoindicateWhetheracacheblockisvalidornotVTagBlockData=HitDataTagIndexoffsetBlockAddressDirectMappedCacheCachehit:blockisstoredinsidecacheIndexisusedtoaccesscacheblockAddresstagiscomparedagainststoredtagIfequalandcacheblockisvalidthenhitOtherwise:cachemissIfnumberofcacheblocksis2nnbitsareusedforthecacheindexIfnumberofbytesinablockis2bbbitsareusedfortheblockoffsetIf32bitsareusedforanaddress32–n–bbitsareusedforthetagCachedatasize=2n+bbytesVTagBlockData=HitDataTagIndexoffsetBlockAddressMappinga6-bitMemoryAddressInexample,blocksizeis4bytes/1word(itcouldbemulti-word)Memoryandcacheblocksarethesamesize,unitoftransferbetweenmemoryandcacheMemoryblocks>>Cacheblocks16Memoryblocks/16words/64bytes/6bitstoaddressallbytes4Cacheblocks,4bytes(1word)perblock4MemoryblocksmaptoeachcacheblockBytewithinblock:lowordertwobits,ignore!(nothingsmallerthanablock)Memoryblocktocacheblock,akaindex:middletwobitsWhichmemoryblockisinagivencacheblock,akatag:toptwobits4/20/202649051ByteOffsetWithinBlock

(e.g.,Word)23BlockWithinIndex4MemBlockWithin

BlockTagCaching:ASimpleFirstExample00011011Cache0000xx0001xx0010xx0011xx0100xx0101xx0110xx0111xx1000xx1001xx1010xx1011xx1100xx1101xx1110xx1111xxMainMemoryTagDataQ:Isthememblockincache?Comparethecachetagtothehighorder2memoryaddressbitstotellifthememoryblockisinthecache

(providedasvalidbitisa1)ValidOnewordblocksTwoloworderbitsdefinethebyteintheblock(32bwords)Q:Whereinthecacheisthememblock?Usenext2lowordermemoryaddressbits–theindex–todeterminewhichcacheblock(i.e.,modulothenumberofblocksinthecache)Index4/20/2026Caching:ASimpleFirstExample00011011CacheMainMemoryQ:Whereinthecacheisthememblock?Usenext2lowordermemoryaddressbits–theindex–todeterminewhichcacheblock(i.e.,modulothenumberofblocksinthecache)TagDataQ:Isthememblockincache?Comparethecachetagtothehigh

order2memoryaddressbitstotellifthememoryblockisinthecache

(providedValidbitis1)Valid0000xx0001xx0010xx0011xx0100xx0101xx0110xx0111xx1000xx1001xx1010xx1011xx1100xx1101xx1110xx1111xxOnewordblocksTwoloworderbitsdefinethebyteintheblock(32bwords)(blockaddress)modulo(#ofblocksinthecache)Index4/20/2026Onewordblocks,cachesize=1Kwords(or4KB)

DirectMappedCacheExample20Tag10IndexDataIndexTagValid012...1021102210233130...131211...210Blockoffset20Data32Hit4/20/2026ValidbitensuressomethingusefulincacheforthisindexCompare

TagwithupperpartofAddresstoseeifaHitReaddatafromcacheinsteadofmemoryifaHitComparatorFourwords/block,cachesize=1Kwords

MultiwordBlockDirectMappedCache8IndexDataIndexTagValid012...2532542553130...131211...43210Byteoffset2020TagHitData32BlockoffsetWhatkindoflocalityarewetakingadvantageof?4/20/2026MappinganAddresstoaCacheBlockExampleConsideradirect-mappedcachewith256blocksBlocksize=16bytesComputetag,index,andbyteoffsetofaddress:0x01FFF8ACSolution32-bitaddressisdividedinto:4-bitbyteoffsetfield,becauseblocksize=24=16bytes8-bitcacheindex,becausethereare28=256blocksincache20-bittagfieldByteoffset=0xC=12(leastsignificant4bitsofaddress)Cacheindex=0x8A=138(nextlower8bitsofaddress)Tag=0x01FFF(upper20bitsofaddress)TagIndexoffset4820BlockAddressExampleonCachePlacement&MissesConsiderasmalldirect-mappedcachewith32blocksCacheisinitiallyempty,Blocksize=16bytesThefollowingmemoryaddresses(indecimal)arereferenced: 1000,1004,1008,2548,2552,2556.MapaddressestocacheblocksandindicatewhetherhitormissSolution:1000=0x3E8 cacheindex=0x1E Miss(firstaccess)1004=0x3EC cacheindex=0x1E Hit1008=0x3F0 cacheindex=0x1F Miss(firstaccess)2548=0x9F4 cacheindex=0x1F Miss(differenttag)2552=0x9F8 cacheindex=0x1F Hit2556=0x9FC cacheindex=0x1F HitTagIndexoffset4523BitsinCacheExampleHowmanytotalbitsarerequiredforadirect-mappedcache16KBofdataand4-wordblocks,assuminga32-bitaddress?Answer16KB=4KWord=212wordsOneblock=4words=22wordsNumberofblocks(indexbit)=212÷22=210blocksDatabitsofblock=4×32=128bitsTagbits=address–index-blocksize=32-10–2-2=18bitsValidbit=1bitTotalCachesize=210×(128+18+1)=210×147=147Kbits

=18.4KBItisabout1.15timesasmanyasneededjustforthedata2026/4/2056MappinganAddresstoMultiwordCacheBlockExampleConsideracachewith64blocksandablocksizeof16bytes.Whatblocknumberdoesbyteaddress1200mapto?Answer(Blockaddress)modulo(Numberofcacheblocks)Wheretheaddressoftheblockis75modulo64=11ByteaddressBytesperblock120016==75ByteaddressBytesperblock×ByteperblockByteaddressBytesperblock×Byteperblock+(Byteperblock-1)12001215Notice!!!Here:2026/4/2057FullyAssociativeCacheAblockcanbeplacedanywhereincache

noindexingIfmblocksexistthenmcomparatorsareneededtomatchtagCachedatasize=m

2bbytesm-wayassociativeAddressTagoffsetDataHit====VTagBlockDataVTagBlockDataVTagBlockDataVTagBlockDatamuxSet-AssociativeCacheSet-AssociativeCacheDiagramm-wayset-associativeVTagBlockDataVTagBlockDataVTagBlockDataVTagBlockDataAddressTagIndexoffsetData====muxHitDirect-mappedcaches291231501621833192100123456789101112131415tagdata78120711732128200225taglineindexblockoffsetAddress:01231bit2bits1bitCacheMemoryFully-associativecachestagdatatagblockoffsetAddress:1bit3bitsCache1101301501601802002202400123456789101112131415Memory100120140170190210230250Set-associativecache291231501621833192100123456789101112131415tagdata78120711732128200225tagsetindexblockoffsetAddress:0

1

1bit1bits2bit0000000100100011010001010110011110001001101010111100110111101111SetAssociativeCacheusingthebook’sstyle291231501621833192100123456789101112131415tagdata78120711732128200225tagsetindexblockoffsetAddress:1bit1bits2bittagdataWay1Way201Set-associativecacheexample291231501621833192100123456789101112131415LdR1

M[1]LdR2

M[5]StR2

M[7]StR1

M[4]LdR3

M[0]LdR2

M[8]CacheProcessorVdtagdataR0R1R2R3Memory78120711732128200225Misses:0Hits:

0000065Set-associativecache291231501621833192100123456789101112131415LdR1

M[1]LdR2

M[5]StR2

M[7]StR1

M[4]LdR3

M[0]LdR2

M[8]CacheProcessorVdtagdataR0R1R2R3Memory78120711732128200225Misses:0Hits:

00000Set-associativecache291231501621833192100123456789101112131415LdR1

M[1]LdR2

M[5]StR2

M[7]StR1

M[4]LdR3

M[0]LdR2

M[8]CacheProcessor07829VdtagdataR0R1R2R3Memory78120711732128200225Misses:1Hits:

00100029lruSet-associativecache291231501621833192100123456789101112131415LdR1

M[1]LdR2

M[5]StR2

M[7]StR1

M[4]LdR3

M[0]LdR2

M[8]CacheProcessor07829VdtagdataR0R1R2R3Memory78120711732128200225Misses:1Hits:

00100029lruSet-associativecache291231501621833192100123456789101112131415LdR1

M[1]LdR2

M[5]StR2

M[7]StR1

M[4]LdR3

M[0]LdR2

M[8]CacheProcessor07829VdtagdataR0R1R2R3Memory17115078120711732128200225Misses:2Hits:

000110029lru150Set-associativecache291231501621833192100123456789101112131415LdR1

M[1]LdR2

M[5]StR2

M[7]StR1

M[4]LdR3

M[0]LdR2

M[8]CacheProcessor07829VdtagdataR0R1R2R3Memory17115078120711732128200225Misses:2Hits:

000110029lru150Set-associativecache291231501621833192100123456789101112131415LdR1

M[1]LdR2

M[5]StR2

M[7]StR1

M[4]LdR3

M[0]LdR2

M[8]CacheProcessor07829VdtagdataR0R1R2R3Memory17115078120711732128200225Misses:3Hits:

00011116215011029lru150lruSet-associativecache291231501621833192100123456789101112131415LdR1

M[1]LdR2

M[5]StR2

M[7]StR1

M[4]LdR3

M[0]LdR2

M[8]CacheProcessor07829VdtagdataR0R1R2R3Memory17115078120711732128200225Misses:3Hits:

00011116215011029lru150lruSet-associativecache291231501621833192100123456789101112131415LdR1

M[1]LdR2

M[5]StR2

M[7]StR1

M[4]LdR3

M[0]LdR2

M[8]CacheProcessor07829VdtagdataR0R1R2R3Memory12915078120711732128200225Misses:3Hits:

10111116215011029lru150lruSet-associativecache291231501621833192100123456789101112131415LdR1

M[1]LdR2

M[5]StR2

M[7]StR1

M[4]LdR3

M[0]LdR2

M[8]CacheProcessor07829VdtagdataR0R1R2R3Memory12915078120711732128200225Misses:3Hits:

10111116215011029lru150lruSet-associativecache291231501621833192100123456789101112131415LdR1

M[1]LdR2

M[5]StR2

M[7]StR1

M[4]LdR3

M[0]LdR2

M[8]CacheProcessor07829VdtagdataR0R1R2R3Memory12915078120711732128200225Misses:3Hits:

20111116215011029lru150lru78Set-associativecache291231501621833192100123456789101112131415LdR1

M[1]LdR2

M[5]StR2

M[7]StR1

M[4]LdR3

M[0]LdR2

M[8]CacheProcessor07829VdtagdataR0R1R2R3Memory129