通信及基础工程27

Unit16TextBDigitalSignalProcessorDigitalSignalProcessorAdigitalsignalprocessor(DSP)isaspecializedmicroprocessor(oraSIPblock),withitsarchitectureoptimizedfortheoperationalneedsofdigitalsignalprocessing.TextTextWordsNotesDiscussionHomeThegoalofDSPsisusuallytomeasure,filterand/orcompresscontinuousreal-worldanalogsignals.Mostgeneral-purposemicroprocessorscanalsoexecutedigitalsignalprocessingalgorithmssuccessfully,butdedicatedDSPsusuallyhavebetterpowerefficiencythustheyaremoresuitableinportabledevicessuchasmobilephonesbecauseofpowerconsumptionconstraints.DSPsoftenusespecialmemoryarchitecturesthatareabletofetchmultipledataand/orinstructionsatthesametime.TextTextWordsNotesDiscussionHome1.OverviewDigitalsignalprocessingalgorithmstypicallyrequirealargenumberofmathematicaloperationstobeperformedquicklyandrepeatedlyonaseriesofdatasamples.Signals(perhapsfromaudioorvideosensors)areconstantlyconvertedfromanalogtodigital,manipulateddigitally,andthenconvertedbacktoanalogform.ManyDSPapplicationshaveconstraintsonlatency;thatis,forthesystemtowork,theDSPoperationmustbecompletedwithinsomefixedtime,anddeferred(orbatch)processingisnotviable.TextTextWordsNotesDiscussionHomeMostgeneral-purposemicroprocessorsandoperatingsystemscanexecuteDSPalgorithmssuccessfully,butarenotsuitableforuseinportabledevicessuchasmobilephonesandPDAsbecauseofpowerefficiencyconstraints.Aspecializeddigitalsignalprocessor,however,willtendtoprovidealower-costsolution,withbetterperformance,lowerlatency,andnorequirementsforspecializedcoolingorlargebatteries.TextTextWordsNotesDiscussionHomeThearchitectureofadigitalsignalprocessorisoptimizedspecificallyfordigitalsignalprocessing.Mostalsosupportsomeofthefeaturesasanapplicationsprocessorormicrocontroller,sincesignalprocessingisrarelytheonlytaskofasystem.SomeusefulfeaturesforoptimizingDSPalgorithmsareoutlinedbelow.TextTextWordsNotesDiscussionHome2.Architecture(1)SoftwareBythestandardsofgeneral-purposeprocessors,DSPinstructionsetsareoftenhighlyirregular;whiletraditionalinstructionsetsaremadeupofmoregeneralinstructionsthatallowthemtoperformawidervarietyofoperations,instructionsetsoptimizedfordigitalsignalprocessingcontaininstructionsforcommonmathematicaloperationsthatoccurfrequentlyinDSPcalculations.BothtraditionalandDSP-optimizedinstructionsetsareabletocomputeanyarbitraryoperationbutanoperationthatmightrequiremultipleARMorx86instructionstocomputemightrequireonlyoneinstructioninaDSPoptimizedinstructionset.TextTextWordsNotesDiscussionHomeOneimplicationforsoftwarearchitectureisthathand-optimizedassembly-coderoutinesarecommonlypackagedintolibrariesforre-use,insteadofrelyingonadvancedcompilertechnologiestohandleessentialalgorithms.Evenwithmoderncompileroptimizationshand-optimizedassemblycodeismoreefficientandmanycommonalgorithmsinvolvedinDSPcalculationsarehand-writteninordertotakefulladvantageofthearchitecturaloptimizations.TextTextWordsNotesDiscussionHome1)Instructionsets·multiply–accumulates(MACs,includingfusedmultiply–add,FMA)operations·usedextensivelyinallkindsofmatrixoperations·convolutionforfiltering·dotproduct·polynomialevaluation·FundamentalDSPalgorithmsdependheavilyonmultiply–accumulateperformance·FIRfiltersTextTextWordsNotesDiscussionHome·FastFouriertransform(FFT)·Instructionstoincreaseparallelism:·SIMD[1]·VLIW[2]·superscalararchitecture·Specializedinstructionsformoduloaddressinginringbuffersandbit-reversedaddressingmodeforFFTcross-referencingTextTextWordsNotesDiscussionHome·Digitalsignalprocessorssometimesusetime-stationaryencodingtosimplifyhardwareandincreasecodingefficiency.·Multiplearithmeticunitsmayrequirememoryarchitecturestosupportseveralaccessesperinstructioncycle·Specialloopcontrols,suchasarchitecturalsupportforexecutingafewinstructionwordsinaverytightloopwithoutoverheadforinstructionfetchesorexittestingTextTextWordsNotesDiscussionHome2)Datainstructions·Saturationarithmetic,inwhichoperationsthatproduceoverflowswillaccumulateatthemaximum(orminimum)valuesthattheregistercanholdratherthanwrappingaround(maximum+1doesn'toverflowtominimumasinmanygeneral-purposeCPUs,insteaditstaysatmaximum).Sometimesvariousstickybitsoperationmodesareavailable.·Fixed-pointarithmeticisoftenusedtospeeduparithmeticprocessing·Single-cycleoperationstoincreasethebenefitsofpipeliningTextTextWordsNotesDiscussionHome3)Programflow·Floating-pointunitintegrateddirectlyintothedatapath·Pipelinedarchitecture·Highlyparallelmultiplier–accumulators(MACunits)·Hardware-controlledlooping,toreduceoreliminatetheoverheadrequiredforloopingoperationsTextTextWordsNotesDiscussionHome(2)Hardware1)MemoryarchitectureDSPsareusuallyoptimizedforstreamingdataandusespecialmemoryarchitecturesthatareabletofetchmultipledataand/orinstructionsatthesametime,suchastheHarvardarchitectureorModifiedvonNeumannarchitecture,whichuseseparateprogramanddatamemories(sometimesevenconcurrentaccessonmultipledatabuses).TextTextWordsNotesDiscussionHome2)AddressingandvirtualmemoryDSPsfrequentlyusemulti-taskingoperatingsystems,buthavenosupportforvirtualmemoryormemoryprotection.Operatingsystemsthatusevirtualmemoryrequiremoretimeforcontextswitchingamongprocesses,whichincreaseslatency.TextTextWordsNotesDiscussionHome·Hardwaremoduloaddressing·Allowscircularbufferstobeimplementedwithouthavingtotestforwrapping·Bit-reversedaddressing,aspecialaddressingmode·usefulforcalculatingFFTs·Exclusionofamemorymanagementunit·Memory-addresscalculationunitTextTextWordsNotesDiscussionHome3.HistoryPriortotheadventofstand-aloneDSPchipsdiscussedbelow,mostDSPapplicationswereimplementedusingbit-sliceprocessors.TheAMD2901bit-slicechipwithitsfamilyofcomponentswasaverypopularchoice.TherewerereferencedesignsfromAMD,butveryoftenthespecificsofaparticulardesignwereapplicationspecific.Thesebitslicearchitectureswouldsometimesincludeaperipheralmultiplierchip.ExamplesofthesemultiplierswereaseriesfromTRWincludingtheTDC1008andTDC1010,someofwhichincludedanaccumulator,providingtherequisitemultiply–accumulate(MAC)function.TextTextWordsNotesDiscussionHomeIn1976,RichardWigginsproposedtheSpeak&SpellconcepttoPaulBreedlove,LarryBrantingham,andGeneFrantzatTexasInstrument'sDallasresearchfacility.Twoyearslaterin1978theyproducedthefirstSpeak&Spell,withthetechnologicalcenterpiecebeingtheTMS5100,theindustry'sfirstdigitalsignalprocessor.Italsosetothermilestones,beingthefirstchiptouseLinearpredictivecodingtoperformspeechsynthesis.TextTextWordsNotesDiscussionHomeIn1978,Intelreleasedthe2920asan"analogsignalprocessor".Ithadanon-chipADC/DACwithaninternalsignalprocessor,butitdidn'thaveahardwaremultiplierandwasnotsuccessfulinthemarket.In1979,AMIreleasedtheS2811.Itwasdesignedasamicroprocessorperipheral,andithadtobeinitializedbythehost.TheS2811waslikewisenotsuccessfulinthemarket.TextTextWordsNotesDiscussionHomeIn1980thefirststand-alone,completeDSPs–theNECµPD7720andAT&TDSP1–werepresentedattheInternationalSolid-StateCircuitsConference'80.BothprocessorswereinspiredbytheresearchinPSTN[3]telecommunications.TextTextWordsNotesDiscussionHomeTheAltamiraDX-1wasanotherearlyDSP,utilizingquadintegerpipelineswithdelayedbranchesandbranchprediction.TextTextWordsNotesDiscussionHomeAnotherDSPproducedbyTexasInstruments(TI)[4],theTMS32010presentedin1983,provedtobeanevenbiggersuccess.ItwasbasedontheHarvardarchitecture,andsohadseparateinstructionanddatamemory.Italreadyhadaspecialinstructionset,withinstructionslikeload-and-accumulateormultiply-and-accumulate.Itcouldworkon16-bitnumbersandneeded390nsforamultiply–addoperation.TIisnowthemarketleaderingeneral-purposeDSPs.TextTextWordsNotesDiscussionHomeAboutfiveyearslater,thesecondgenerationofDSPsbegantospread.Theyhad3memoriesforstoringtwooperandssimultaneouslyandincludedhardwaretoacceleratetightloops,theyalsohadanaddressingunitcapableofloop-addressing.Someofthemoperatedon24-bitvariablesandatypicalmodelonlyrequiredabout21nsforaMAC.MembersofthisgenerationwereforexampletheAT&TDSP16AortheMotorola56000.TextTextWordsNotesDiscussionHomeThemainimprovementinthethirdgenerationwastheappearanceofapplication-specificunitsandinstructionsinthedatapath,orsometimesascoprocessors.Theseunitsalloweddirecthardwareaccelerationofveryspecificbutcomplexmathematicalproblems,liketheFourier-transformormatrixoperations.Somechips,liketheMotorolaMC68356,evenincludedmorethanoneprocessorcoretoworkinparallel.OtherDSPsfrom1995aretheTITMS320C541ortheTMS320C80.TextTextWordsNotesDiscussionHomeThefourthgenerationisbestcharacterizedbythechangesintheinstructionsetandtheinstructionencoding/decoding.SIMDextensionswereadded,VLIWandthesuperscalararchitectureappeared.Asalways,theclock-speedshaveincreased,a3nsMACnowbecamepossible.TextTextWordsNotesDiscussionHome4.ModernDSPsModernsignalprocessorsyieldgreaterperformance;thisisdueinparttobothtechnologicalandarchitecturaladvancementslikelowerdesignrules,fast-accesstwo-levelcache,(E)DMAcircuitryandawiderbussystem.NotallDSPsprovidethesamespeedandmanykindsofsignalprocessorsexist,eachoneofthembeingbettersuitedforaspecifictask,ranginginpricefromaboutUS$1.50toUS$300.TexasInstrumentsproducestheC6000seriesDSPs,whichhaveclockspeedsof1.2GHzandimplementseparateinstructionanddatacaches.(tobecontinued)TextTextWordsNotesDiscussionHome(Continued)Theyalsohavean8MiB2ndlevelcacheand64EDMAchannels.Thetopmodelsarecapableofasmanyas8000MIPS(instructionspersecond),useVLIW(verylonginstructionword),performeightoperationsperclock-cycleandarecompatiblewithabroadrangeofexternalperipheralsandvariousbuses(PCI/serial/etc).TMS320C6474chipseachhavethreesuchDSPs,andthenewestgenerationC6000chipssupportfloatingpointaswellasfixedpointprocessing.TextTextWordsNotesDiscussionHomeFreescale[5]producesamulti-coreDSPfamily,theMSC81xx.TheMSC81xxisbasedonStarCoreArchitectureprocessorsandthelatestMSC8144DSPcombinesfourprogrammableSC3400StarCoreDSPcores.EachSC3400StarCoreDSPcorehasaclockspeedof1GHz.TextTextWordsNotesDiscussionHomeXMOSproducesamulti-coremulti-threadedlineofprocessorwellsuitedtoDSPoperations.Theycomeinvariousspeedsrangingfrom400to1600MIPS.Theprocessorshaveamulti-threadedarchitecturethatallowsupto8real-timethreadspercore,meaningthata4coredevicewouldsupportupto32realtimethreads.Threadscommunicatebetweeneachotherwithbufferedchannelsthatarecapableofupto80Mbit/s.ThedevicesareeasilyprogrammableinCandaimatbridgingthegapbetweenconventionalmicro-controllersandFPGAs.TextTextWordsNotesDiscussionHomeCEVA,Inc.producesandlicensesthreedistinctfamiliesofDSPs.PerhapsthebestknownandmostwidelydeployedistheCEVA-TeakLiteDSPfamily,aclassicmemory-basedarchitecture,with16-bitor32-bitword-widthsandsingleordualMACs.TheCEVA-XDSPfamilyoffersacombinationofVLIWandSIMDarchitectures,withdifferentmembersofthefamilyofferingdualorquad16-bitMACs.TheCEVA-XCDSPfamilytargetsSoftware-definedRadio(SDR)modemdesignsandleveragesauniquecombinationofVLIWandVectorarchitectureswith3216-bitMACs.TextTextWordsNotesDiscussionHomeAnalogDevicesproducetheSHARC-basedDSPandrangeinperformancefrom66MHz/198MFLOPS(millionfloating-pointoperationspersecond)to400MHz/2400MFLOPS.SomemodelssupportmultiplemultipliersandALUs,SIMDinstructionsandaudioprocessing-specificcomponentsandperipherals.TheBlackfinfamilyofembeddeddigitalsignalprocessorscombinethefeaturesofaDSPwiththoseofageneraluseprocessor.Asaresult,theseprocessorscanrunsimpleoperatingsystemslikeµCLinux,velOSityandNucleusRTOSwhileoperatingonreal-timedata.TextTextWordsNotesDiscussionHomelatencyn.潜伏；潜在因素deferv.使推迟；使延期；延期；服从arbitraryadj.[数]任意的；武断的；专制的assemblyn.装配；集会，集合compilern.[计]编译程序；汇编者matrixn.[数]矩阵；模型WordsWordsTextWordsNotesDiscussionHomeconvolutionn.[数]卷积；回旋；盘旋；卷绕polynomialn.[数]多项式superscalarn.超标量体系结构saturationn.饱和；色饱和度；磁化饱和moduloprep.&adv.以…为模；按模计算peripheraladj.&n.外围的；次要的；外部设备WordsTextWordsNotesDiscussionHomemilestonen.里程碑，划时代的事件operandn.[计]操作数；[计]运算对象leveragen.&v.杠杆作用；利用；举债经营WordsTextWordsNotesDiscussionHome[1]SIMD（SingleInstructionMultipleData），单指令多数据流，能够复制多个操作数，并把它们打包在大型寄存器的一组指令集。TextWordsNotesDiscussionNotesHome[2]VLIW（VeryLongInstructionWord）是一种非常长的指令组合，它把许多条指令连在一起，增加了运算的速度。VLIW体系结构是美国Multiflow和Cydrome公司于20世纪80年代设计的体系结构，EPIC体系结构就是从VLIW中衍生出来的。TextWordsNotesDiscussionHome[3]PSTN（PublicSwitchedTelephoneNetwork）：公共交换电话网络，一种常用旧式电话系统，即我们日常生活中常用的电话网。TextWordsNotesDiscussionHome[4]Texa