数字设计课件 第6章 组合逻辑设计实践2

Chapter6CombinationalLogicDesignPracticesMSIbuildingblocksaretheimportantelementofcombinationalcircuits.5/14/20261本章重点具备一定功能的通用组合逻辑电路的设计方法及实例掌握常用的MSI的使用方法及功能扩展掌握译码器、MUX实现组合逻辑功能的方法能分析、设计由MSI构建的电路5/14/20262chapter66.1DocumentationStandard1.SignalNamesandActiveLevelsMostsignals(signalname)haveactivelevel.

activehighactivelowNamingconvention

surffix“_L”attachingtosignalnamerepresentactivelowlevel.Like,EN_L、READY_L……Inlogicrelation,EN_L=EN’，READY_L=READY’。5/14/20263chapter62.ActivelevelsforpinsENEN_LDinstartDoutflgstart_LDinDoutflg_LInversionbubbleActivelowENENDinstartDoutflgstartDinDoutflgActivehign5/14/20264chapter6Exp2：①EN=1(activehigh),datacanbetransferred②EN=0(activelow),datacanbetransferredENCLKEN_LCLK5/14/20265chapter63.bubble-to-bubblelogicdesignMakethelogiccircuiteasiertounderstand.Exp：NotmatchABSELDATAABASELDATAmatch5/14/20266chapter66.3CombinationalPLDs1.Programmablelogicarrays(PLA)twolevel“AND—OR”device.Canbeprogrammedtorealizeanysum-of-productslogicexpression.Ann×m

PLAwithpproductterms:n—inputsm—outputsp—productterms5/14/20267chapter64×3with6producttermsANDarrayORarray5/14/20268chapter65/14/20269chapter62.ProgrammableArrayLogicDevicesFixedORarray，programmableANDarrayBidirectionalinput/outputpins，熔丝型PAL16L8，Outputenable5/14/202610chapter63.GenericArrayLogicDevices（GAL）aninnovationofthePAL;canbeerasedandreprogrammed;5/14/202611chapter66.4DecoderAnimportanttypeofcombinationalcircuit.inputcodeword

enableinputOutputcodeword

decodeer1-to-1mapping1-out-of-mcoden<mn-bitm-bit5/14/202612chapter61、bianrydecodersinputcode：n-bitoutputcode：2n-bit⑴2-4decoder（2-22）

I1I0Y3Y2Y1Y0truthtable：？Yi：？I1I0Y3Y2Y1Y0000001010010100100111000Yi=miY0=I1’·I0’ Y1=I1’·I0Y2=I1·I0’ Y3=I1·I02-4decoderOneinputcombinationchoosesanoutputport.5/14/202613chapter62-4decoderwithenableinputYi=EN·miENI1I0Y3Y2Y1Y00××00001000001101001011001001111000I1I0Y3Y2Y1Y0EN2-4decoder5/14/202614chapter6（2）74×139,dual2-4decoderInputcode：B（MSB）

A（LSB）Alsobecalledaddressinput.Outputcode：Y3_L~Y0_LEN5/14/202615chapter6（3）74××138,3-8decoderEnableinputEN=G1·G2A_L’·G2B_L’Inputcode：C（MSB）、B、AOutputcode：

Y0_L~Y7_LYi_L=（EN·mi）’Y0_LY1_LY2_LY3_LY4_LY5_LY6_LY7_LG1G2A_LG2B_LEN5/14/202616chapter6ENmsblsb5/14/202617chapter62、realizingcombinationalcircuitswithdecoderreview：canonicalsumDecoderoutput：Yi_L=(EN·mi)’whenEN=1，Yi_L=mi’=MiaddanNANDgatetothedecoder’soutput.Exp:(1)F=∑AB（0、3）F=A’·B’+A·BEnableasserted5/14/202618chapter6（2）ifa3-bitnumberXYZisoddnumber，thenODDoutput1，elseoutput0.realizethefunctionwithdecoderandgates.solution：F=？F=ΣXYZ（1，3，5，7）5/14/202619chapter6（3）F=∏XYZ（0、1、5）

解：5/14/202620chapter63.CascadingbinarydecodersHowtoconstructa4-16、5-32……decoder？

usemultiple2-4or3-8decoderstocascade.PS.：confirmthenumberofdecodersaccordingtotheinputandoutputbits.onlyonechipworksineachdecodingoperation.5/14/202621chapter6Exp：a4-16decoderInputs:4-bitN3、N2、N1、N0。Outputs:16-bitDEC15_L~DEC0_LNeed23-8decoders.

UsetheMSBoftheinputsaschip-selectbit. 0000

0001 0111… 1000

1001… 1111N3N2N1N0N3N2N1N05/14/202622chapter6Chipselecting5/14/202623chapter6Exp：4-bitprime-numberdetector.Realizingitwith74×138andsomegates.N3N2N1N0F5/14/202624chapter64、7-segmentdecoderClassifyof7-segdisplayer：inmaterials:LED（发光二极管）

LCD（液晶）Inworkingmode:common-cathode(共阴极)common-anode(共阳极)afbcegddpabcdedpfggndgnd5/14/202625chapter67-segmentdecodertransformtheinputBCDcodeto7-segmentdisplayingcode.devices：

7446A、74LS47（驱动共阳）

74LS48、74LS49（驱动共阴）0000~1001areusefulinputcodes.1010~1111areunusedBCDcode.5/14/202626chapter674LS495/14/202627chapter65、BCDdecoder（二—十进制译码器）Inputs:BCDY0Y9……BCDdecoderOutput:1-out-of10code74HC425/14/202628chapter65.5Encoder1、binaryencoder…………

inputs:1-out-of-2n

codeI0I1Im(m=2n-1)……

output:n-bitY0Y1Yn-1binaryencoder5/14/202629chapter68-3encoderinputoutputI7I6I5I4I3I2I1I0Y2Y1Y01000000011101000000110001000001010001000010000001000011000001000100000001000100000001000In/out:activehigh5/14/202630chapter6Y0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I5+I6+I7Eachinputporthasitscorrespondingoutputcode.5/14/202631chapter62、PriorityEncoderifmultipleinputsareasserted,howtodealwith?solution：assignprioritytoeachinputfromhightolow.letI7—highestpriorityanddecreasefromI6downtoI0A2,A1,A0—encodeoutputIDLE—whennoinputisasserted,IDLE=15/14/202632chapter6inputoutputI7I6I5I4I3I2I1I0A2A1A0IDLE1×××××××111001××××××1100001×××××10100001××××100000001×××0110000001××01000000001×00100000000100000000000000015/14/202633chapter6LogicexpressionsforpriorityencoderH7=I7H6=I6·I7’H5=I5·I6’·I7’……H0=I0·I1’·I2’·I3’·I4’·I5’·I6’·I7’A2=H4+H5+H6+H7A1=H2+H3+H6+H7A0=H1+H3+H5+H7IDLE=(I0+I1+I2+I3+I4+I5+I6+I7)’=I0’·I1’·I2’·I3’·I4’·I5’·I6’·I7’ExpressionsforeachassertedinputinthetruthtableofpriorityencoderOutputcodeexpressions5/14/202634chapter63、74××148PriorityEncoderEI_L：EnableInput.I7_L~I0_L：encodeinput，I7_Lhashighestpriority.A2_L~A0_L：encodeoutputGS_L：GS_L=0whenoneormoreoftherequestinputsareasserted.EO_L：enableoutput,EO_L=0whenalloftherequestinputsarenegativeandEI_L=0.高低优先级5/14/202635chapter674××148真值表5/14/202636chapter64、cascadingpriorityencoderproblem：howtoconstruct16-4、32-5……priorityencoder？Connectingmultiple8-3endoder.note：makesuretheneedednumberofchipsaccordingtotheinputs.needtoredesigntheoutputcircuitthatcouldproducethecorrectencodingoutput.5/14/202637chapter616-4priorityencoder:usetwo74××148U1、U2，(1)U1:inputE15_L~E8_L;U2:inputE7_L~E0_L;E15_Listhehighestpriority,(2)output:A3_L~A0_L，activelow;(3)Whenoneormoreinputsisasserted，GS0_L=0；andA3_L~A0_L=1111.5/14/202638chapter616-4priorityencoderU174HC148A09A110A211GS14D34D45D56D23D12D78D67EI12EO13U274HC148A09A110A211GS14D34D45D56D23D12D01D78D67EI12EO13U3A74HC08U3B74HC08U3C74HC08U3D74HC08D01EN15_LEN14_LEN13_LEN12_LEN11_LEN10_LEN9_LEN8_LEN7_LEN6_LEN5_LEN4_LEN3_LEN2_LEN1_LEN0_LD0_LD1_LD2_LD3_LGS_L5/14/202639chapter6思考：若需要编码输出、GS0为高电平有效，如何修改电路输出结构？P.413figure6-49showsthe32-5priorityencoder’sstrcture,.5/14/202640chapter66.6Three-stateDevices1、three-statebuffers5/14/202641chapter6EN_LAOUTENEN_LAAOUT_LOUT_LEnablemeans:thebufferoutputnormallogic0、1whenENisasserted；thebufferoutputHi-ZwhenENisnegated.5/14/202642chapter6Applicationdata返回时序

addressofdatasource5/14/202643chapter6IssuesinapplicationTPLZ、TPHZ：timethattakesfromnormallogicintoHi-Z;TPZL、TPZH

：timethattakesfromHi-Zintonormallogic;generally，TPLZ、TPHZ<TPZL、TPZH

Buttoconfirmthecorrectioninapplication,acontrollogicisadopted.5/14/202644chapter674××

138的相关引脚信号查看电路

截止时间

（停滞时间）5/14/202645chapter6课堂练习试设计一个电路，当控制信号M=1时，电路为“判一致”电路，即当三个输入变量取值全部相同时输入为1；当控制信号M=0时，电路为“多数表决”电路，即输出等于输入变量中占多数的取值。请写出最简表达式。（注：至少要写出卡诺图，三变量为X、Y、Z）5/14/202646chapter66.7Multiplexer2-to-1MUXABSELYY=SEL’·A+SEL·BS=0，Y=AS=1，Y=BABS=0Y=AABS=1Y=BLogiccircuit5/14/202647chapter6又称数据选择器，简称MUXOutput:enableselect

ndatasource

dataoutput

n≤2s

mj：SEL[j]minterm1、基本结构：5/14/202648chapter6Letb=1,D0D1DjDn-1SELENY……5/14/202649chapter6Exp:4-to-1MUXABCDS1S001101234outputCS0S1output00A01B10C11D5/14/202650chapter62、MSIMUX（1）8-to-1MUX，74××151EN_LaddressY_LY5/14/202651chapter6返回5/14/202652chapter6G_L

S（2）4-bit,2inputMUX，74××1575/14/202653chapter6（3）2bit,4inputMUX，74××153inputoutput1G_L2G_LBA1Y2Y00001C02C000011C12C100101C22C200111C32C301001C0001011C1001101C2001111C30100002C0100102C1101002C2101102C311××001G_L2G_L5/14/202654chapter63、ExpandingMUXsExp1：use74××151torealizea16-to-1MUX,somegatescanbeusedifnecessary.Chipsneeded：

accordingtothe16inputs,274××151chips.output：

combinetwochip’soutputsintooneoutput.5/14/202655chapter6TheMSB(A3)ofinputactasthechip-selectbit.5/14/202656chapter6Exp2：用74××153实现4输入，4位MUX，。设4路输入分别是：1D[3..0]、2D[3..0]、3D[3..0]、4D[3..0]；

4位输出是：Dout[3..0]

输入选择：S1、S0解：无需外加门，只需要合理安排输入、输出数据端口即可。5/14/202657chapter6Dout3S1S05/14/202658chapter64、用MUX实现组合逻辑函数的标准和

multipleinput,1bitMUX,theoutput：

whenENisasserted：

thecanonicalsumform.74×151的内部电路mj:mintermoftheselect(address)inputs.5/14/202659chapter6MUX的数据输入端与真值表的每行输出对应，MUX的地址选择端作为最小项产生器，即

真值表：输出值 输入变量

MUX：数据输入端 地址端Exp1：acircuitoutput1whenits3-bitinputcanbedividedby3.constructthecircuitbyusing74××151.So：F=∑XYZ（？）

andcircuit？按最小项编号顺序变量与选择端对应5/14/202660chapter6例1的电路XYZFU1~W6D04D13D22D31D415D514D613D712S011S29S110Y5~G7VCCGNDR15/14/202661chapter6例2：若例1中输入数为4位二进制数，如何实现？解1：用16输入，1位的MUX来实现，选用74××150。F=∑WXYZ（0，3，6，9，12，15）解2：仍选用74××151，先对所求函数的卡诺图做降维处理。预备知识：卡诺图的降维

用一个n变量的卡诺图来处理m变量的函数（n<m），这种卡诺图被称为降维（降次）的卡诺图。它允许单元格中除了0、1、无关项外，还可包含单变量或逻辑表达式。5/14/202662chapter6卡诺图的降维卡诺图降次的过程：设m=n+1，在m-变量函数F(X1,X2,…,Xn,Xn+1)中选择一个“入图”的变量Xi，用剩下的n个变量构造n-变量卡诺图。原图中变量Xi取值相反所覆盖的相邻的两个单元格被合并。（这两个单元格的其余变量是相同的；在真值表中对应着两行，只有Xi是不同的，其余变量均相同。）00011110FWXYZ000111WYZX10选择入图将被合并5/14/202663chapter6降维的基本步骤①先建新的真值表，表中的输入变量是除Xi而外剩下的变量，新行号由他们的组合值（最小项）确定。②若在原(n+1)变量真值表中，被合并的两行的入图变量Xi与对应的F取值相同，则新表中F=XiWXYZFFnew×××00Z×××11W、X、Y取值相同5/14/202664chapter6③若在原(n+1)变量真值表中，被合并的两行的入图变量Xi与对应的F取值相反，则新表中F=Xi’④若在原(n+1)变量真值表中，被合并的两行的入图变量Xi所对应的F=1，则新表中F=1⑤若在原(n+1)变量真值表中，被合并的两行的入图变量Xi所对应的F=0，则新表中F=0⑥得新的n变量卡诺图⑦用MUX实现5/14/202665chapter6输入输出WXYZF0000100010001000011101000010100110101110输入输出WXYZF1000010011101001011011001110101110011111新输出FZ’Z0Z’0123新编号4567新编号新输出FZ0Z’Z5/14/202666chapter6卡诺图中降维原4变量卡诺图 新3变量卡诺图1000010100011110F00100101WXYZ000111WYZX100ZZ’ZZZ’0Z’WXFnewYWYX5/14/202667chapter6例2的电路图U1~W6D04D13D22D31D415D514D613D712S011S29S110Y5~G7GNDIO1U2AZZ’WXYF5/14/202668chapter65.Multiplexers、DemultiplexersandBusesdemultiplexersDin……

2nbitparalleloutputdemultiplexers…1-bitD0D1Dm最多m=2nSELn-bitNoDeMUXchips,abinarydecoderwithenableinputcanbeusedasaDeMUX.5/14/202669chapter6MUX、DeMUX应用于数据的选择与分配MUX：combinemparallel-inputdatasourcesintoserialoutputdata.DeMUX：routethebusdatato1ofmdestinations.MUXDe

-MUX……SRCASRCBSRCCSRCZSRCSELBUSDSTSELDSTADSTBDSTCDSTZ5/14/202670chapter6（1）MUX：parallel—serialconversion

8-to-1

MUXD0D1D2D3D4D5D6D7S2S1S0t5/14/202671chapter65/14/202672chapter6（2）DeMUX:serial—parallelconversionUsea74××138asaDeMUX.5/14/202673chapter6DiagramofExp.S2S1S0111110101100011010001000010101015/14/202674chapter66.8Exclusive-ORgatesandParitycircuits1、XORandXNORgatesXYX⊕Y(X⊕Y)’XORXNOR0001011010101101（X⊙Y）XORXNOR记忆：异或门—相同为0，相异为1

异或非门—与异或相反5/14/202675chapter6PropertiesX⊕0=X

X⊕1=X’X⊕X=0

X⊕X’=1X⊕Y=Y⊕XX⊕Y⊕Z=(X⊕Y)⊕Z=X⊕(Y⊕Z)Equivalentsymbols

Anytwosignals(inputsoroutputs)ofanXORorXNORgatemaybecomplementedwithoutchangingtheresultinglogicfunction.5/14/202676chapter6FeatureofXORexpression(k-map)X⊕Y⊕Z=X’YZ’+XY’Z’+X’Y’Z+XYZFXYZ0

1

01101000011110XY01Z010100001111XYZ5/14/202677chapter62、paritycircuitsCascadenXORgatestoforman+1inputsodd-paritycircuit.Itmeansthatitsoutput1ifanoddnumberofitsinputsare1.ODD=I1⊕I2⊕……⊕In

Daisy-chainconnection5/14/202678chapter6Complementtheoutputofodd-paritycircuit，itcanworksasanEven-paritywhichoutput1ifanevennumberofitsinputare1.Treestructure，hasfasteroperationspeed.5/14/202679chapter6奇偶校验的实现奇偶校验码(补充)

由n位信息位+1位奇偶校验位(paritybit)构成。偶校验编码：n位信息码中包含奇数个1，则偶校验位(evenparitybit)

置为1，使总的1的个数是偶数个

。奇校验编码：n位信息码中包含偶数个1，则奇校验位(oddparitybit)

置为1，使总的1的个数是奇数个

。5/14/202680chapter6Exp：someacircuitadaptoddparity,ifinputdatais3-bit,pleasegivetheparity-bitgenerator.B200001111B100110011B001010101P10010110inputoutput5/14/202681chapter63、74×2809-bitparitygeneratorGeneratetheparitybitwhenacodewordisstoredortransmitted.Checktheparitybitwhenacodewordisretrievedorreceived.EVEN=A⊕B⊕C⊕D⊕E⊕F⊕(G⊕H⊕I)’ODD=A⊕B⊕C⊕D⊕E⊕F⊕G⊕H⊕I5/14/202682chapter61databufferdataPINmemoryWRRDRDWRPOUTERROR0101ODD=A⊕B⊕C⊕D⊕E⊕F⊕G⊕H⊕I=PIN=POUT2EN5/14/202683chapter66.9Comparatorscomparator—comparestwobinarynumberandindicateswhethertheyareequal.Magnitudecomparator—interpretthebinarynumberassignedorunsignednumbersandalsoindicateanarithmeticrelationship(greateroflessthan).5/14/202684chapter61、structureofcomparator（1）1-bitcomparator（2）multiple-bitcomparatorparallelcomparatoriterativecomparatorDIFF=A0⊕B0EQ=（A0⊕B0）’5/14/202685chapter6Parallelcomparator4-bitparallelcomparatorIterativecomparator(serialcomparator)5/14/202686chapter62.IterativeCircuitCascadenidenticalmodulesboundaryoutputCICOPIPOC0C1PI0PO0CICOPIPOPI1PO1CICOPIPOPIn-1POn-1CnC2…Cn-1boundaryinputscascadinginputcascadingoutput5/14/202687chapter6comparatormoduleiterativecomparatorEQIEQOXY1X0Y0EQIEQOXYX1Y1EQ1EQ2…EQIEQOXYXn-1Yn-1EQnlowerspeed,butbeeasytoexpand5/14/202688chapter63.Magnitudecomparators（1）1-bitmagnitudecomparatorsABF(A>B)F(A=B)F(A<B)00010010011010011010FA>B=AB’FA<B=A’BFA=B=A’B’+ABABFA>BFA<BFA=B5/14/202689chapter6（2）multiple-bitMagnitudecomparators2-bit，inputA[1..0]、B[1..0]A1B1A0B0FA>BFA=BFA<B01××110××100001000110010100111110011101111101111115/14/202690chapter6

FA>B=(A1>B1)+(A1=B1)·(A0>B0)

=A1·B1’+(A’B’+AB)·(A1·B1’)FA=B=(A1=B1)·(A0=B0)FA<B=(A1<B1)+(A1=B1)·(A0<B0)A1B1A0B0FA>BFA=BFA<BA1<B1××1A1>B1××1A1=B1A0<B01A1=B1A0>B01A1=B1A0=B01Pseudo-logic5/14/202691chapter64.StandardMSImagnitudecomparator74×85:4-bitMagnitudeinput:A[3..0],B[3..0]Cascadinginput：ALBI、AEBI、AGBI，whichareusedtoexpandingcomparator.output：ALBO、AEBO、AGBOAGBO=(A>B)+(A=B)·AGBIAEBO=(A=B)·AEBIALBO=(A<B)+(A=B)·ALBI5/14/202692chapter6Cascadingmagnitudecomparator

inserialmode:iterativecomparatorFA>BFA=BFA<B5/14/202693chapter6

inparallelmodeFA>BFA=BFA<BX[11..8]Y[11..8]X[7..4]Y[7..4]X[3..0]Y[3..0]5/14/202694chapter6ClassexerciseABCDFD’AA’DC’D’C’ABJudgewhetherthefollowingcircuithasstatichazardornot,ifstatichazardexist,pleasepointitandeliminatebyusingK-map.Thenwritethehazardlessminimalsum.5/14/202695chapter66.10Adders、Subtractorsand