VHDL语言语言组合逻辑电路设计课件

VHDL語言語言組合邏輯電路設計

一、邏輯門電路設計例1：用數據流描述方式設計一個4輸入“與或非”邏輯門LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYyhf4IS PORT(A,B,C,D: INSTD_LOGIC; Y: OUTSTD_LOGIC);ENDyhf4;ARCHITECTUREdata_flowOFyhf4ISBEGIN Y<=NOT((AANDB)OR(CANDD));ENDdata_flow;請畫出電路圖例2：設計一雙向8位匯流排驅動器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYqd8IS PORT( A,B: INOUTSTD_LOGIC_VECTOR(7DOWNTO0); EN,DIR:INSTD_LOGIC);ENDqd8;ARCHITECTUREbehaviorOFqd8ISSIGNALAOUT,BOUT:STD_LOGIC_VECTOR(7DOWNTO0);BEGINAB:PROCESS(A,EN,DIR) IF((EN=‘0’)AND(DIR=‘1’)THEN BOUT<=A; ELSE BOUT<=“ZZZZZZZZ”; ENDIF;B<=BOUT;ENDPROCESSAB;為什麼定義信號？BA:PROCESS(B,EN,DIR) IF((EN=‘0’)AND(DIR=‘0’)THEN AOUT<=B; ELSE AOUT<=“ZZZZZZZZ”; ENDIF;ENDPROCESSBA;A<=AOUTENDbehavior;例2：設計一雙向8位匯流排驅動器二編碼器設計例1：設計8－3優先權編碼器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYbmq83IS PORT(D: INSTD_LOGIC_VECOR(7DOWNTO0); Y: OUTSTD_LOGIC_VECTOR(2DOWNTO0));ENDbmq83;ARCHITECTUREbehaviorOFbmq83ISBEGINPROCESS(D) BEGIN IFD(7)=‘0’THENY<=“000”; ELSIFD(6)=‘0’THENY<=“001”; ELSIFD(5)=‘0’THENY<=“010”; ELSIFD(4)=‘0’THENY<=“011”; ELSIFD(3)=‘0’THENY<=“100”; ELSIFD(2)=‘0’THENY<=“101”; ELSIFD(1)=‘0’THENY<=“110”; ELSIFD(0)=‘0’THENY<=“111”; ELSY<=“XXX”;ENDPROCESS;ENDbehavior;該描述具有優先順序三解碼器設計例1：設計3－8線解碼器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYymq83IS PORT(A,B,C: INSTD_LOGIC; Y:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDymq83;請注意數據類型的聲明ARCHITECTUREbehaviorOFymq83ISSIGNALINDATA:STD_LOGIC_VECTOR(2DOWNTO0);BEGININDATA<=C&B&A; PROCESS(INDATA) BEGIN CASEINDATAIS WHEN“000”=>Y<=“11111110”; WHEN“001”=>Y<=“11111101”; WHEN“010”=>Y<=“11111011”; WHEN“011”=>Y<=“11110111”; WHEN“100”=>Y<=“11101111”; WHEN“101”=>Y<=“11011111”; WHEN“110”=>Y<=“10111111”; WHEN“111”=>Y<=“01111111”; WHENOTHERS=>Y<=“XXXXXXXX”; ENDCASE;ENDPROCESS;ENDbehavior;該描述不具有優先順序例1：設計3－8線解碼器解碼器設計四、運算器設計例1：設計4位二進位加法器數據類型必須一致才能賦值LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYjfq4IS PORT(a,b: INSTD_LOGIC_VECOR(3DOWNTO0); sum: OUTSTD_LOGIC_VECTOR(4DOWNTO0));ENDjfq4;ARCHITECTUREbehaviorOFjfq4ISBEGINPROCESS(a,b) BEGIN sum<=(‘0’&a)+(‘0’&b);ENDPROCESS;ENDbehavior;例2：設計8位整數加法器將數據類型轉換為一致LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYjfq8IS PORT(op1,op2:INUNSIGNED(3DOWNTO0); result: OUTINTEGER);ENDjfq8;ARCHITECTUREbehaviorOFjfq8ISBEGINresult<=CONV_INTEGER(OP1+OP2);ENDbehavior;四、運算器設計五、奇偶校驗電路設計例1：設計9位奇偶校驗電路，輸入數據中“1”的個數為奇數時輸出為“0”，否則輸出為“1”。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYjou9IS PORT(a: INSTD_LOGIC_VECTOR(8DOWNTO0); y: OUTSTD_LOGIC);ENDjou9;ARCHITECTUREbehaviorOFymq83ISBEGINPROCESS(a) VARIABLEtemp:STD_LOGIC;BEGINtemp:=1;FORiIN0TO8LOOPtemp:=tempXORa(i);ENDLOOP;ENDPROCESS;y<=temp;ENDbehavior;能否定義為信號？例1：設計9位奇偶校驗電路，輸入數據中“1”的個數為奇數時輸出為“0”，否則輸出為“1”。奇偶校驗電路設計六、已知真值表邏輯設計方法例1：設計4選1數據選擇器。方法一：採用CASE語句LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYxzq4_1IS PORT(a,b: INSTD_LOGIC; i0,i1,i2,i3: INSTD_LOGIC; f: OUTSTD_LOGIC);ENDxzq4_1;ARCHITECTUREbehaviorOFymq83ISSIGNALsel:STD_LOGIC_VECTOR(1DOWNTO0);BEGIN

sel<=B&A;PROCESS(sel) BEGIN CASEselIS WHEN“00”=>F<=i0; WHEN“01”=>F<=i1; WHEN“10”=>F<=i2; WHEN“11”=>F<=i3; WHENOTHERS=>NULL; ENDCASE;ENDbehavior;為什麼有OTHERS？已知真值表邏輯設計方法方法二：採用條件信號代入語句ARCHITECTUREbehaviorOFymq83ISSIGNALsel:STD_LOGIC_VECTOR(1DOWNTO0);BEGIN

sel<=B&A; f<=i0WHENsel=“00”ELSE i1WHENsel=“01”ELSE i2WHENsel=“10”ELSE i3WHENsel=“11”ELSE ‘X’;ENDbehavior;並行or順序描述？已知真值表邏輯設計方法方法三：採用IF語句ARCHITECTUREbehaviorOFymq83ISSIGNALsel:STD_LOGIC_VECTOR(1DOWNTO0);BEGIN

sel<=B&A;

PROCESS(sel) BEGIN IFsel=“00”THENf<=i0; ELSIFsel=“01”THENf<=i1; ELSIFsel=“10”THENf<=i2; ELSIFsel=“11”THENf<=i3; ENDIF; ENDPROCESSENDbehavior;有無優先順序？已知真值表邏輯設計方法方法四：採用選擇信號代入語句ARCHITECTUREbehaviorOFymq83ISSIGNALsel:STD_LOGIC_VECTOR(1DOWNTO0);BEGIN

sel<=B&A; WITHselSELECT f<=i0WHENsel=“00” i1WHENsel=“01” i2WHENsel=“10” i3WHENsel=“11” ‘X’WHENOTHERS;ENDbehavior;並行or順序描述？已知真值表邏輯設計方法七、已知邏輯運算式設計方法例1：設計1位全加器。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYqjq1IS PORT(A,B,C,CIN: INSTD_LOGIC; SUM,COUT: OUTSTD_LOGIC);ENDqjq1;ARCHITECTUREdata_flowOFqjq1ISBEGINPROCESS(A,B,CIN)BEGINCOUT<=(AANDB)OR(AANDCIN)OR(BANDCIN);ENDPROCESS;SUM<=AXORBXORCIN;ENDdata_flow;注意優先順序八、已知邏輯電路設計方法例1：已知2－4線解碼器電路。請用數據流的方式設計LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYymq24IS PORT(A0,A1: INSTD_LOGIC; Y0,Y1,Y2,Y3: OUTSTD_LOGIC);ENDymq24;ARCHITECTUREdata_flowOFymq24ISBEGIN PROCESS(A0,A1) BEGIN Y0<= Y1<= Y2<= Y3<= ENDPROCESS;ENDdata_flow; Y0<=NOT((NOTA1)AND(NOTA0)); Y1<=NOT((NOTA1)ANDA0); Y2<=NOT(A1AND(NOTA0)); Y3<=NOT(A1ANDA0);已知邏輯電路設計方法L1L2L3L4添加中間信號已知邏輯電路設計方法ARCHITECTUREdataflowOFymq24IS COMPONENTGINV PORT(A:INSTD_LOGIC; C:OUTSTD_LOGIC); ENDCOMPONENT; COMPONENTGNAND2 PORT(A,B:INSTD_LOGIC; C:OUTSTD_LOGIC); ENDCOMPONENT; SIGNALL1,L2,L3,L4:STD_LOGIC;BEGIN

U1:GINVPORTMAP(A0,L1); U2:GINVPORTMAP(A1,L