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1、2020/6/18,.,集成电路设计流程和EDA工具CAEDAEDA技术经理傅红军,2020/6/18,.,集成电路设计流程和EDA工具,ContentofPresentation设计流程FunctionalVerificationSynthesisTimingTestingP例子:形式验证(formalverification)静态时序分析(statictiminganalysis),2020/6/18,.,集成电路设计流程和EDA工具,SimulationSoftwaretosimulatecircuitbehaviorinvirtualtime(processeventssequenti

2、ally)CoverBehavior,RTLandgateslevelPros:flexibleeasydebuggingtransparent,2020/6/18,.,集成电路设计流程和EDA工具,SimulationEvent-DrivenSimulationCycleBaseSimulationCompliedCodeLogicSimulation,2020/6/18,.,集成电路设计流程和EDA工具,SimulationAccelerationUsespecialhardwaretosimulatecircuitbehaviorinvirtualtimeTraditionallyonl

3、ycovergatelevelRTLtechnologyisgettingmatureandwellaccepted,2020/6/18,.,集成电路设计流程和EDA工具,EmulatiomUsemirrorhardwaretomimiccircuitbehaviorDesignerareacceptingemulationPros:forlatedesignstagebeforetapeoutfastcanconnecttorealtimesystemprototyping,2020/6/18,.,集成电路设计流程和EDA工具,EmulatiomCons:moreexpensivediffi

4、culttouse,timingusersneeditfromearlystagedebugging,2020/6/18,.,集成电路设计流程和EDA工具,形式验证(FormalVerification)通过数学的方法证明不同层次设计的等效性;传统的验证方法:,2020/6/18,.,集成电路设计流程和EDA工具,形式验证(FormalVerification)形式验证方法:,spec,Designcreation,RTL,DesignImplementation,Gate,PhysicalImplementation,GDSII,形式验证(FormalVerification)形式验证方法:

5、,EquivalenceChecker,EquivalenceChecker,2020/6/18,.,集成电路设计流程和EDA工具,ContentofPresentation设计流程FunctionalVerificationSynthesisTimingTestingPnostructureResynthesis:concernsthedatapath,resourceallocationandassignmentcanbeimprovedbasedonmoredetailedKnowledgeaboutphysicalcharacteristcsofalernateimplementati

6、on,2020/6/18,.,集成电路设计流程和EDA工具,RegisterLevelSynthesis(cont.)RegisterRelocation:modifiestheinitialassignmentofoperationtocontrolstepsbystructuralchangesRe-timing:optimizestheperformanceHDLSynthesis:Correcttranslationofcycle-by-cyclebehaviorintofunctionallyequivalentsetofequations,2020/6/18,.,集成电路设计流程和

7、EDA工具,LogicLevelSynthesis(cont.)LogiclevelSynthesisThemainpointisoptimization,logic-minimizationAimingtheminimalarea(measuredasnumberofliterals)MappingMapthegroupsofabstractgatestomatchingphysicallibrarycellsofagiventargettechnology,2020/6/18,.,综合的具体过程,Synthesis=Translation+Optimization+Mapping,Resi

8、due0);If(high_bits=“10”)thenresidue0);Endif;,Translation,Optimize+Map,GTECH:通用库,目标库,2020/6/18,.,综合的目的,提高效率,抽象,利用技巧,再利用,容易验证,容易移植,提高自身,2020/6/18,.,RTL综合的简单过程,2020/6/18,.,集成电路设计流程和EDA工具,PhysicalSynthesis物理综合=synthesis+placement+optimization在深亚微米设计中,考虑连线的延迟,加速时序收敛,2020/6/18,.,基于物理综合流程概述,RTL,Synthesis(D

9、C),Floorplan(SE),CellPlacement(PC),CTGEN&Routing(SE),RCextraction(HyperExtract),Verification(backannotation),STA(PT),DRC&LVS(Dracula),Tapeout,DC:DesignCompilerPC:PhysicalCompilerSE:SiliconEnsemblePT:PrimeTime,DRC:DesignRuleCheckLVS:LayoutVersusSchematicSTA:StaticTimingAnalysis,2020/6/18,.,集成电路设计流程和E

10、DA工具,ContentofPresentation设计流程FunctionalVerificationSynthesisTimingTestingP&RPhysicalChecking/ExtractionEDATools,2020/6/18,.,集成电路设计流程和EDA工具,StaticTimingAnalysisAmethodfordeterminingifacircuitmeetstimingconstraintswithouthavingtosimulateclockcyclesDesignsarebrokendownintosetsoftimingpathsThedelayofea

11、chpathiscalculatedAllpathdelaysarecheckedtoseeiftimingconstraintshavebeenmeet,2020/6/18,.,集成电路设计流程和EDA工具,StaticTimingVerificationTocheckthepotentialtimingviolationsetuptimeholdtimepulsewidthclockskewcheckingetc.,2020/6/18,.,集成电路设计流程和EDA工具,ContentofPresentation设计流程FunctionalVerificationSynthesisTimin

12、gTestingP&RPhysicalChecking/ExtractionEDATools,2020/6/18,.,VLSIRealizationProcess,Determinerequirements,Writespecifications,DesignsynthesisandVerification,Fabrication,Manufacturingtest,Chipstocustomer,Customersneed,Testdevelopment,2020/6/18,.,Verificationvs.Test,Verifiescorrectnessofdesign.Performed

13、bysimulation,hardwareemulation,orformalmethods.Performedoncepriortomanufacturing.Responsibleforqualityofdesign.,Verifiescorrectnessofmanufacturedhardware.Two-partprocess:1.Testgeneration:softwareprocessexecutedonceduringdesign2.Testapplication:electricaltestsappliedtohardwareTestapplicationperformed

14、oneverymanufactureddevice.Responsibleforqualityofdevices.,2020/6/18,.,DFT(Design-for-Test),Scanstuck-at/DCDelay/ACLogicBIST(Built-inSelf-Test)MemoryBISTiddq,2020/6/18,.,Scanpath扫描路径法,扫描路径法是一种规则的可测试性设计方法,适用于时序电路。其设计思想是把电路中的关键节点连接到一个移位寄存器上,当作为扫描路径的移位寄存器处于串入/并出状态时,可以用来预置电路的状态。当作为扫描路径的移位寄存器处于并入/串出状态时,可以

15、把内部节点的状态依次移出寄存器链。,2020/6/18,.,集成电路设计流程和EDA工具,ContentofPresentation设计流程FunctionalVerificationSynthesisTimingTestingP&RPhysicalChecking/ExtractionEDA,2020/6/18,.,集成电路设计流程和EDA工具,ContentofPresentation设计流程FunctionalVerificationSynthesisTimingTestingP&RPhysicalChecking/ExtractionEDATools,2020/6/18,.,集成电路设

16、计流程和EDA工具,PhysicalCheckingDesignChecksPerformedAfterP&RBeforeFabricationRelatedtoSpacing,Connections,ViasElectricalChecksPerformedDuringP&RFocusonShortCircuit,OpenCircuitandFloatingNodesLVSPerformedAfterP&RToEnsureFinalPhysicalLayoutIsconsistentToInputNetlist,2020/6/18,.,CircuitExtraction,Convertlay

17、outgeometrytocircuitnetlistdevicessometimesconverttogatesconnectivityparasiticsGoalverifythatlayoutmatchescircuitassumelayoutpassesDRCdetermineactualcircuitparasiticsback-annotateandresimulateuseminimumCPUtime,memoryintegratedextractor+layouteditoruseexistingdatastructuresextractinteractively,2020/6

18、/18,.,40,EDAtools,2020/6/18,.,RespondentsuseEDAtoolsforavarietyoffunctions,2020/6/18,.,CadenceandSynopsystoolsarecurrentlymostused,2002,2020/6/18,.,AboutCAEDA,CAEDA致力于为科研,企业,教育等部门提供国际上最新、最先进的EDA设计,以及集成电路设计咨询和解决方案CAEDA业务包括三个方面:设计咨询服务ConsultancyEDA和CAE销售CAE/EDAsoftwaredistribution培训课程Trainingcourses,2

19、020/6/18,.,CAEDAEDA产品介绍,ADiT数模混合电路级仿真解决方案DesignCraft逻辑综合工具DesignCraftPro物理综合工具TimeCraft静态时序分析工具Laker全定制版图工具DebussyHDL调试工具SpecmantElite自动化系统功能验证工具,2020/6/18,.,SPICEINPUTDECK,Verilog(HDL),Parser&Partition,MOSFETTable,Debussy(nWave),ADiT-PLOT,ADiT-Engine,SPICE,Turbo,MOT,HDL,Veritools(undertow),VPI,ADiT

20、Analog,DigitalTurboSimulator,2020/6/18,.,LakerL3fullcustomICdesign,DesignbrowserEasilytraversedesignManipulatelogichierarchytooptimizeforlayoutpurposeD&DdevicestocreatelayoutSchematicgeneratorForm-gateanduserdefinedsymbolsmakeitmorereadablethanCDLnetlistHelplayoutplanningLayoutwindowFlightlinestoshowtheconnectivityReal-timeshortdetectorCrossprobing,2020/6/18,.,Verification=Detection+Debug,ChangeCode,SimulateAgain,Capture,Intent,Detect,Errors,Debug,Capture,Design,Verilog,VHDL,Testb

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