基于VHDL的数字时钟课程设计

1、 数字时钟设计1.设计要求(1)能显示周、时、分、秒，精确到0.1秒(2)可自行设置时间(3)可设置闹铃，并且对闹铃时间长短可控制2.设计分析 （1）根据题目要求可分解为正常计时、时间设置和闹铃设置三大模块 （2）正常计时模块可分解为周、时、分、秒等子模块 （3）时间设置模块分别进行秒置数、分置数、时置数和周置数 （4）闹铃设置模块分解为闹钟判定和闹铃时长设定3.设计结构图时间重置闹钟设定数字钟正常计数数字显示4.设计流程图开始正常计时重置时间？否是时重置分重置秒重置正常计时时间重置？是否设置闹钟？时设定分设定时刻到达？是响铃时间显示-Second1(秒计数 6进制和10进制) Library

2、 ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity second1 is Port( clks,set:in std_logic;s1,s0:in std_logic_vector(3 downto 0); Secs,Secg: buffer std_logic_vector(3 downto 0); cout1:out std_logic); End second1; Architecture a of second1 is Begin Process(clks,set) variable s

3、s,sg: std_logic_vector(3 downto 0);-(ss:秒十位；sg秒个位)variable co: std_logic; Begin If set=1 then ss:=s1; sg:=s0; Elsif clksevent and clks=1 then if ss=0101 and sg=1001 then ss:=0000; sg:=0000;co:=1; elsif sg1001 then sg:=sg+1;co:=0; elsif sg=1001 then sg:=0000;ss:=ss+1;co:=0; end if; end if; cout1=co;-

4、 （进位信号）Secs=ss; Secg=sg; end process; End a;仿真波形图：-Min1（分计数器 6进制和10进制 alm实现整点报时） Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity min1 is Port(clkm,set:in std_logic;m1:in std_logic_vector(3 downto 0);m0:in std_logic_vector(3 downto 0); mins,ming:out std_logic_vector

5、(3 downto 0); enmin,alarm: out std_logic); End; Architecture a of min1 is Begin Process(clkm,set) variable ms,mg :std_logic_vector(3 downto 0); variable so,alm :std_logic; Begin if set=0 then ms:=m1;mg:=m0; Elsif clkmevent and clkm=1 then if ms=0101 and mg=1001 then ms:=0000;mg:=0000; so :=1; alm:=1

6、; elsif mg1001 then mg:=mg+1; so :=0;alm:=0; elsif mg=1001 then mg:=0000;ms:=ms+1; so :=0;alm:=0; end if; end if; alarm=alm; enmin= so; mins=ms; ming=mg; End process; End a;仿真波形图：-Hour1（时计数器 4进制与2进制） Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity hour1 is Port(clk

7、h,set:in std_logic;h1,h0:in std_logic_vector(3 downto 0); hours,hourg:buffer std_logic_vector(3 downto 0);enhour: out std_logic);End; Architecture a of hour1 is Begin Process(clkh,set) variable hs,hg :std_logic_vector(3 downto 0);variable ho:std_logic; Begin If set=1 then hs:=h1; hg:=h0; Elsif clkhe

8、vent and clkh=1 then if hs=0010and hg=0011 then hs:=0000;hg:=0000; ho :=1;elsif hg1001 then hg:=hg+1; ho :=0;elsif hg=1001 then hg:=0000;hs:=hs+1; ho :=0;end if; end if; hours=hs; hourg=hg;enhour=ho;End process; End a;仿真波形图：Library ieee; (星期计数器，7进制)Use ieee.std_logic_1164.all;Use ieee.std_logic_arit

9、h.all;Use ieee.std_logic_unsigned.all;Entity week is Port(clkd,set,reset:in std_logic;d1:in std_logic_vector(3 downto 0); - 置数端（星期）day:buffer std_logic_vector(3 downto 0); - 星期输出端end;Architecture a of week is Begin Process(clkd,reset,set,d1) Begin If reset=0 then day=0000; - 对星期计时器清0 Elsif set=0 the

10、n day=d1; - 对星期计时器置d1的数 Elsif clkdevent and clkd=1 thenIf day=6 then day=0000; - 重复计数 Else day=day+1;End if; End if; End process;End;仿真波形图：-Second2(秒置数模块， 6进制和10进制) Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity second2 is Port( clks1:in std_logic;Secs,Secg: out s

11、td_logic_vector(3 downto 0); End; Architecture a of second2 is Begin Process(clks1) variable ss,sg: std_logic_vector(3 downto 0);-(ss:秒十位；sg秒个位)Begin if clks1event and clks1=1 then if ss=0101 and sg=1001 then ss:=0000; sg:=0000;elsif sg1001 then sg:=sg+1; elsif sg=1001 then sg:=0000;ss:=ss+1;end if;

12、 end if; Secs=ss; Secg=sg; end process; End a;仿真波形图：-Min2（分置数模块， 6进制和10进制） Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity min2 is Port(clkm1:in std_logic;mins,ming:buffer std_logic_vector(3 downto 0); End; Architecture a of min2 is Begin Process(clkm1) variable ms

13、,mg :std_logic_vector(3 downto 0); Begin if clkm1event and clkm1=1 then if ms=0101 and mg=1001 then ms:=0000;mg:=0000;elsif mg1001 then mg:=mg+1;elsif mg=1001 then mg:=0000;ms:=ms+1;end if; end if; mins=ms; ming=mg; End process; End a;仿真波形图：-Hour2（时置数模块， 4进制与2进制） Library ieee; Use ieee.std_logic_116

14、4.all; Use ieee.std_logic_unsigned.all; Entity hour2 is Port(clkh1:in std_logic;hours,hourg:buffer std_logic_vector(3 downto 0);End; Architecture a of hour2 is Begin Process(clkh1) variable hs,hg :std_logic_vector(3 downto 0);Begin if clkh1event and clkh1=1 then if hs=0010and hg=0011 then hs:=0000;h

15、g:=0000;elsif hg1001 then hg:=hg+1;elsif hg=1001 then hg:=0000;hs:=hs+1;end if; end if; hours=hs; hourg=hg;End process; End a;仿真波形图：Library ieee; （星期置数模块，7进制）Use ieee.std_logic_1164.all;Use ieee.std_logic_arith.all;Use ieee.std_logic_unsigned.all;Entity week2 is Port(clkd1:in std_logic;day:buffer st

16、d_logic_vector(3 downto 0); - 星期输出端end;Architecture a of week2 is Begin Process(clkd1) Begin if clkd1event and clkd1=1 thenIf day=6 then day=0000; - 重复计数 Else day=day+1;End if; End if; End process;End;仿真波形图：library ieee; （闹钟设置模块）use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity nz i

17、sport(ml,mh:in std_logic_vector(3 downto 0); hl,hh:in std_logic_vector(3 downto 0); mlo,mho:in std_logic_vector(3 downto 0); hlo,hho:in std_logic_vector(3 downto 0); set:in std_logic; output:out std_logic);end nz;architecture behav of nz is signal opt:std_logic;beginprocess(set,ml,mh,hl,hh,mlo,mho,h

18、lo,hho)beginif set=1 thenif(ml=mlo and mh=mho and hl=hlo and hh=hho)thenopt=1;else opt=0;end if;end if;output=opt;end process;end behav;library ieee; （闹钟响铃时长设置）use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity timeset is port( nz:in std_logic; sj:in integer range 0 to 1200; clk:in std_logic; ring:out std_logic);