西电verilog课件第十章

1、7/3/2020,1,MicroelectronicsSchoolXidianUniversity,第10章VerilogHDL高级程序设计,10.1乘法器设计,7/3/2020,2,MicroelectronicsSchoolXidianUniversity,10.1.1Wallace树乘法器,7/3/2020,3,MicroelectronicsSchoolXidianUniversity,图10.1-2Wallace树乘法器结构图,7/3/2020,4,MicroelectronicsSchoolXidianUniversity,modulewallace(x,y,out);parame

2、tersize=4;/Defineparametersinputsize-1:0 x,y;output2*size-1:0out;/IOdeclarationwiresize*size-1:0a;wire1:0b0,b1,c0,c1,c2,c3;/Wiredeclarationwire5:0add_a,add_b;wire6:0add_out;wire2*size-1:0out;assigna=x3,x3,x2,x2,x1,x3,x1,x0,x3,x2,x1,x0,x2,x1,x0,x0/Prepartmultiplier,haddU1(.x(a8),.y(a9),.out(b0);/2inp

3、uthalfadderhaddU2(.x(a11),.y(a12),.out(b1);haddU3(.x(a4),.y(a5),.out(c0);faddU4(.x(a6),.y(a7),.z(b00),.out(c1);/3inputfulladderfaddU5(.x(a13),.y(a14),.z(b01),.out(c2);faddU6(.x(b10),.y(a10),.z(b11),.out(c3);assignadd_a=c31,c21,c11,c01,a3,a1;/adderassignadd_b=a15,c30,c20,c10,c00,a2;assignadd_out=add_

4、a+add_b;assignout=add_out,a0;endmodule,7/3/2020,5,MicroelectronicsSchoolXidianUniversity,modulefadd(x,y,z,out);output1:0out;inputx,y,z;assignout=x+y+z;endmodulemodulehadd(x,y,out);output1:0out;inputx,y;assignout=x+y;endmodule,modulewallace_tb;reg3:0 x,y;wire7:0out;wallacem(.x(x),.y(y),.out(out);/mod

5、uleinstanceinitial/Stimulisignalbeginx=3;y=4;#20 x=2;y=3;#20 x=6;y=8;endendmodule,10.1.2复数乘法器,7/3/2020,6,MicroelectronicsSchoolXidianUniversity,7/3/2020,7,MicroelectronicsSchoolXidianUniversity,例10.1-1：用VerilogHDL设计实部和虚部均为4位2进制书的复数乘法器,modulecomplex(a,b,c,d,out_real,out_im);input3:0a,b,c,d;output8:0o

6、ut_real,out_im;wire7:0sub1,sub2,add1,add2;wallaceU1(.x(a),.y(c),.out(sub1);wallaceU2(.x(b),.y(d),.out(sub2);wallaceU3(.x(a),.y(d),.out(add1);wallaceU4(.x(b),.y(c),.out(add2);assignout_real=sub1-sub2;assignout_im=add1+add2;endmodule,modulecomplex_tb;reg3:0a,b,c,d;wire8:0out_real;wire8:0out_im;complex

7、U1(.a(a),.b(b),.c(c),.d(d),.out_real(out_real),.out_im(out_im);initialbegina=2;b=2;c=5;d=4;#10a=4;b=3;c=2;d=1;#10a=3;b=2;c=3;d=4;endendmodule,10.1.3向量乘法器,7/3/2020,8,MicroelectronicsSchoolXidianUniversity,7/3/2020,9,MicroelectronicsSchoolXidianUniversity,例10.1-2：用VerilogHDL设计一个4维向量乘法器,modulevector(a1

8、,a2,a3,a4,b1,b2,b3,b4,out);input3:0a1,a2,a3,a4,b1,b2,b3,b4;outputwire9:0out;wire7:0out1,out2,out3,out4;wire8:0out5,out6;wallacem1(.x(a1),.y(b1),.out(out1);wallacem2(.x(a2),.y(b2),.out(out2);wallacem3(.x(a3),.y(b3),.out(out3);wallacem4(.x(a4),.y(b4),.out(out4);assignout5=out1+out2;assignout6=out3+out

9、4;assignout=out5+out6;endmodule,modulevector_tb;reg3:0a1,a2,a3,a4;reg3:0b1,b2,b3,b4;wire9:0out;initialbegina1=2b10;a2=2b10;a3=2b10;a4=2b10;b1=2b10;b2=2b10;b3=2b10;b4=2b10;endvectorm(.a1(a1),.a2(a2),.a3(a3),.a4(a4),.b1(b1),.b2(b2),.b3(b3),.b4(b4),.out(out);endmodule,10.1.4查找表乘法器,7/3/2020,10,Microelec

10、tronicsSchoolXidianUniversity,表10.1-122位的乘法查找表,modulelookup(out,a,b,clk);output3:0out;input1:0a,b;inputclk;reg3:0out;reg3:0address;always(posedgeclk)beginaddress=a,b;case(address)4b0000:out=4b0000;4b0001:out=4b0000;4b0010:out=4b0000;4b0011:out=4b0000;4b0100:out=4b0000;,4b0101:out=4b0001;4b0110:out=4

11、b0010;4b0111:out=4b0011;4b1000:out=4b0000;4b1001:out=4b0010;4b1010:out=4b0100;4b1011:out=4b0110;4b1100:out=4b0000;4b1101:out=4b0011;4b1110:out=4b0110;4b1111:out=4b1001;default:out=4bx;endcaseendendmodule,7/3/2020,11,MicroelectronicsSchoolXidianUniversity,modulelookup_mult(out,a,b,clk);output7:0out;i

12、nput3:0a,b;inputclk;reg7:0out;reg1:0firsta,firstb,seconda,secondb;wire3:0outa,outb,outc,outd;always(posedgeclk)beginfirsta=a3:2;seconda=a1:0;firstb=b3:2;secondb=b1:0;endlookupm1(.out(outa),.a(firsta),.b(firstb),.clk(clk);lookupm2(.out(outb),.a(firsta),.b(secondb),.clk(clk);lookupm3(.out(outc),.a(sec

13、onda),.b(firstb),.clk(clk);lookupm4(.out(outd),.a(seconda),.b(secondb),.clk(clk);always(posedgeclk)beginout=(outa4)+(outb2)+(outc2)+outd;endendmodule,modulelookup_mult_tb;reg3:0a,b;regclk=0;wire7:0out;integeri,j;always#10clk=clk;lookup_multm1(.out(out),.a(a),.b(b),.clk(clk);initialbegina=0;b=0;for(i

14、=1;i15;i=i+1)#20a=i;endinitialbeginfor(j=1;j15;j=j+1)#20b=j;endinitialbegin#360$stop;endendmodule,10.2FIFOVerilogHDL实现,7/3/2020,12,MicroelectronicsSchoolXidianUniversity,7/3/2020,13,MicroelectronicsSchoolXidianUniversity,例10.2-1：用VerilogHDL设计深度为128，位宽为8的FIFO,moduleFIFO_buffer(clk,rst,write_to_stack,

15、read_from_stack,Data_in,Data_out);inputclk,rst;inputwrite_to_stack,read_from_stack;input7:0Data_in;output7:0Data_out;wire7:0Data_out;wirestack_full,stack_empty;wire2:0addr_in,addr_out;FIFO_controlU1(.stack_full(stack_full),.stack_empty(stack_empty),.write_to_stack(write_to_stack),.write_ptr(addr_in)

16、,.read_ptr(addr_out),.read_from_stack(read_from_stack),.clk(clk),.rst(rst);ram_dualU2(.q(Data_out),.addr_in(addr_in),.addr_out(addr_out),.d(Data_in),.we(write_to_stack),.rd(read_from_stack),.clk1(clk),.clk2(clk);endmodule,7/3/2020,14,MicroelectronicsSchoolXidianUniversity,moduleFIFO_control(write_pt

17、r,read_ptr,stack_full,stack_empty,write_to_stack,read_from_stack,clk,rst);parameterstack_width=8;parameterstack_height=8;parameterstack_ptr_width=3;outputstack_full;/stackfullflagoutputstack_empty;/stackemptyflagoutputstack_ptr_width-1:0read_ptr;/readdataaddressoutputstack_ptr_width-1:0write_ptr;/wr

18、itedataaddressinputwrite_to_stack;/writedatatostackinputread_from_stack;/readdatafromstackinputclk;inputrst;regstack_ptr_width-1:0read_ptr;regstack_ptr_width-1:0write_ptr;regstack_ptr_width:0ptr_gap;regstack_width-1:0Data_out;regstack_width-1:0stackstack_height-1:0;,7/3/2020,15,MicroelectronicsSchoo

19、lXidianUniversity,/stackstatussignalassignstack_full=(ptr_gap=stack_height);assignstack_empty=(ptr_gap=0);always(posedgeclkorposedgerst)if(rst)beginData_out=0;read_ptr=0;write_ptr=0;ptr_gap=0;endelseif(write_to_stackendelseif(!write_to_stackptr_gap=ptr_gap-1;endelseif(write_to_stackendendmodule,7/3/

20、2020,17,MicroelectronicsSchoolXidianUniversity,moduleram_dual(q,addr_in,addr_out,d,we,rd,clk1,clk2);output7:0q;/outputdatainput7:0d;/inputdatainput2:0addr_in;/writedataaddresssignalinput2:0addr_out;/outputdataaddresssignalinputwe;/writedatacontrolsignalinputrd;/readdatacontrolsignalinputclk1;/writed

21、ataclockinputclk2;/readdataclockreg7:0q;reg7:0mem7:0;/8*8bitesregisteralways(posedgeclk1)beginif(we)memaddr_in=d;endalways(posedgeclk2)beginif(rd)q=memaddr_out;endendmodule,7/3/2020,18,MicroelectronicsSchoolXidianUniversity,moduleFIFO_tb;regclk,rst;reg7:0Data_in;regwrite_to_stack,read_from_stack;wir

22、e7:0Data_out;FIFO_bufferU1(.clk(clk),.rst(rst),.write_to_stack(write_to_stack),.read_from_stack(read_from_stack),.Data_in(Data_in),.Data_out(Data_out);initialbeginclk=0;rst=1;Data_in=0;write_to_stack=1;read_from_stack=0;#5rst=0;#155write_to_stack=0;read_from_stack=1;endalways#10clk=clk;initialbeginr

23、epeat(7)#20Data_in=Data_in+1;endendmodule,7/3/2020,19,MicroelectronicsSchoolXidianUniversity,10.3log函数的VerilogHDL实现,7/3/2020,20,MicroelectronicsSchoolXidianUniversity,表10.3-1log函数计算表,例10.3-1用VerilogHDL设计采用查找表方式的log函数，输入信号位宽4bits，输出信号位宽8bits。,modulelog_lookup(x,clk,out);input3:0 x;inputclk;output7:0o

24、ut;reg7:0out;always(posedgeclk)begincase(x)4b1000:out=8b00000000;4b1001:out=8b00000111;4b1010:out=8b00001110;4b1011:out=8b00010101;4b1100:out=8b00011001;4b1101:out=8b00100000;4b1110:out=8b00100100;4b1111:out=8b00101000;default:out=8bz;endcaseendendmodule,输入数据为一位整数位三位小数位精确到2-3，输出结果两位整数位六位小数位精确到2-6。,7

25、/3/2020,21,MicroelectronicsSchoolXidianUniversity,modulelog_lookup_tb;regclk;reg3:0 x;wire7:0out;initialbeginx=4b1000;clk=1b0;repeat(7)#10 x=x+1;endalways#5clk=clk;log_lookupU1(.x(x),.clk(clk),.out(out);endmodule,7/3/2020,22,MicroelectronicsSchoolXidianUniversity,例10.3-2用VerilogHDL设计采用泰勒级数展开方式的log函数

26、，输入信号位宽4bits，输出信号位宽8bits。,7/3/2020,23,MicroelectronicsSchoolXidianUniversity,modulelog(x,out);input3:0 x;output7:0out;wire3:0out1;wire7:0out2,out3,out5,out;wire3:0out4;assignout4=out37:4;assignout1=x-4b1000;/(x-1)wallaceU1(.x(out1),.y(4b0111),.out(out2);/0.43*(x-1)wallaceU2(.x(out1),.y(out1),.out(ou

27、t3);/(x-1)2wallaceU3(.x(out4),.y(4b0011),.out(out5);/0.22*(x-1)2assignout=out2-out5;/0.43*(x-1)-0.22*(x-1)2endmodule,modulelog_tb;reg3:0 x=4b1000;wire7:0out;logU1(.x(x),.out(out);always#10 x=x+1;always(x)beginif(x=4b0000)$stop;endendmodule,10.4数字频率计,7/3/2020,24,MicroelectronicsSchoolXidianUniversity

28、,数字频率计是一种可以测量信号频率的数字测量仪器，它常常用来测量方波信号、正弦信号、三角波信号以及其他各种单位时间内变化的物理量。在数字电路中，数字频率计属于时序电路，主要由触发器构成。,例10.4-1设计一个8位数字显示的简易频率计。要求：能够测试10Hz10MHz方波信号；电路输入的基准时钟为1Hz，要求测量值以8421BCD码形式输出；系统有复位键；,7/3/2020,25,MicroelectronicsSchoolXidianUniversity,modulefreqDetect(clk_1Hz,fin,rst,d0,d1,d2,d3,d4,d5,d6,d7);inputclk_1H

29、z,fin,rst;output3:0d0,d1,d2,d3,d4,d5,d6,d7;wire3:0q0,q1,q2,q3,q4,q5,q6,q7;wire3:0d0,d1,d2,d3,d4,d5,d6,d7;/控制模块controlcontrol(.clk_1Hz(clk_1Hz),.rst(rst),.count_en(count_en),.latch_en(latch_en),.clear(clear);/计数器模块counter_10counter0(.en_in(count_en),.clear(clear),.rst(rst),.fin(fin),.en_out(en_out0),

30、.q(q0);counter_10counter1(.en_in(en_out0),.clear(clear),.rst(rst),.fin(fin),.en_out(en_out1),.q(q1);counter_10counter2(.en_in(en_out1),.clear(clear),.rst(rst),.fin(fin),.en_out(en_out2),.q(q2);,counter_10counter3(.en_in(en_out2),.clear(clear),.rst(rst),.fin(fin),.en_out(en_out3),.q(q3);counter_10cou

31、nter4(.en_in(en_out3),.clear(clear),.rst(rst),.fin(fin),.en_out(en_out4),.q(q4);counter_10counter5(.en_in(en_out4),.clear(clear),.rst(rst),.fin(fin),.en_out(en_out5),.q(q5);counter_10counter6(.en_in(en_out5),.clear(clear),.rst(rst),.fin(fin),.en_out(en_out6),.q(q6);counter_10counter7(.en_in(en_out6)

32、,.clear(clear),.rst(rst),.fin(fin),.en_out(en_out7),.q(q7);/锁存器模块latchu1(.clk_1Hz(clk_1Hz),.rst(rst),.latch_en(latch_en),.q0(q0),.q1(q1),.q2(q2),.q3(q3),.q4(q4),.q5(q5),.q6(q6),.q7(q7),.d0(d0),.d1(d1),.d2(d2),.d3(d3),.d4(d4),.d5(d5),.d6(d6),.d7(d7);endmodule,7/3/2020,26,MicroelectronicsSchoolXidianU

33、niversity,7/3/2020,27,MicroelectronicsSchoolXidianUniversity,modulecontrol(clk_1Hz,rst,count_en,latch_en,clear);inputclk_1Hz,rst;outputcount_en,latch_en,clear;regcount_en,latch_en,clear;reg1:0state;always(posedgeclk_1Hzornegedgerst)if(!rst)beginstate=2d0;count_en=1b0;latch_en=1b0;clear=1b0;endelsebe

34、gincase(state)2d0:begincount_en=1b1;latch_en=1b0;clear=1b0;state=2d1;end2d1:begincount_en=1b0;latch_en=1b1;clear=1b0;state=2d2;end2d2:begincount_en=1b0;latch_en=1b0;clear=1b1;state=2d0;enddefault:begincount_en=1b0;latch_en=1b0;clear=1b0;state=2d0;endendcaseendendmodule,7/3/2020,28,MicroelectronicsSc

35、hoolXidianUniversity,modulecounter_10(counter_enrst,clear,fin,en_out,q);inputcounter_en,rst,fin,clear;outputen_out;output3:0q;regen_out;reg3:0q;always(posedgefinornegedgerst)if(!rst)beginen_out=1b0;q=4b0;endelseif(counter_en)beginif(q=4b1001)beginq=4b0;en_out=1b1;endelsebeginq=q+1b1;en_out=1b0;enden

36、delseif(clear)beginq=4b0;en_out=1b0;endelsebeginq=q;en_out=1b0;endendmodule,7/3/2020,29,MicroelectronicsSchoolXidianUniversity,modulelatch(clk_1Hz,latch_en,rst,q0,q1,q2,q3,q4,q5,q6,q7,d0,d1,d2,d3,d4,d5,d6,d7);inputrst,clk_1Hz,latch_en;input3:0q0,q1,q2,q3,q4,q5,q6,q7;output3:0d0,d1,d2,d3,d4,d5,d6,d7;

37、reg3:0d0,d1,d2,d3,d4,d5,d6,d7;always(posedgeclk_1Hzornegedgerst)if(!rst)begind0=4b0;d1=4b0;d2=4b0;d3=4b0;d4=4b0;d5=4b0;d6=4b0;d7=4b0;endelseif(latch_en)begind0=q0;d1=q1;d2=q2;d3=q3;d4=q4;d5=q5;d6=q6;d7=q7;endelsebegind0=d0;d1=d1;d2=d2;d3=d3;d4=d4;d5=d5;d6=d6;d7=d7;endendmodule,7/3/2020,30,Microelect

38、ronicsSchoolXidianUniversity,timescale1ns/1psmodulefreqDetect_tb;parameterCLK1HZ_DELAY=5_0000_0000;/1Hz基准信号parameterFIN_DELAY=100;/5MHz的被测频率regclk_1Hz;regfin;regrst;wire3:0d0,d1,d2,d3,d4,d5,d6,d7;Initialbeginrst=1b0;#1rst=1b1;endInitialbeginfin=1b0;forever#FIN_DELAYfin=fin;endInitialbeginclk_1Hz=1b0

39、;forever#CLK1HZ_DELAYclk_1Hz=clk_1Hz;endfreqDetectU1(.clk_1Hz(clk_1Hz),.rst(rst),.fin(fin),.d0(d0),.d1(d1),.d2(d2),.d3(d3),.d4(d4),.d5(d5),.d6(d6),.d7(d7);endmodule,10.6巴克码相关器设计,7/3/2020,31,MicroelectronicsSchoolXidianUniversity,巴克码是50年代初，R.H.巴克提出的一种具有特殊规律的二进制码组。它是一个非周期序列，一个n位的巴克码X1，X2，X3，Xn)，每个码元只可

40、能取值+1或-1。而11位的巴克码则是11b11100010010。,modulebarc(clk,rst,din,valid);inputclk,rst,din;outputvalid;reg10:0shift;wire10:0f;wire1:0sum1,sum2,sum3,sum4,sum5;wire2:0sum6,sum7;regvalid;wire3:0sum;always(posedgeclkornegedgerst)if(!rst)shift=11b0;elseshift=shift9:0,din;,assignf=shift11b11100010010;assignsum1=f0

41、+f1;assignsum2=f2+f3;assignsum3=f4+f5;assignsum4=f6+f7;assignsum5=f8+f9+f10;assignsum6=sum1+sum2;assignsum7=sum3+sum4+sum5;assignsum=sum6+sum7;always(sum)if(sum=10)valid=1b1;elsevalid=1b0;endendmodule,7/3/2020,32,MicroelectronicsSchoolXidianUniversity,modulebarc_tb;regclk,rst,din;reg32:0data;Initial

42、beginclk=1b0;forever#10clk=clk;endInitialbeginrst=1b0;#5rst=1b1;endInitialdata=33b11100010011_11100010001_11100010010;integeri;always(posedgeclkornegedgerst)if(!rst)din=1b0;i=32;elseif(i=0)din=datai;i=32;elsedin=datai;i=i-1;barcm(.clk(clk),.rst(rst),.din(din),.valid(valid);endmodule,10.7FIR滤波器设计,7/3

43、/2020,33,MicroelectronicsSchoolXidianUniversity,10.7.1FIR滤波器VerilogHDL实现,7/3/2020,34,MicroelectronicsSchoolXidianUniversity,moduleFIR(Data_out,Data_in,clock,reset);output9:0Data_out;input3:0Data_in;inputclock,reset;wire9:0Data_out;wire3:0samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,sa

44、mples_6,samples_7,samples_8;shift_registerU1(.Data_in(Data_in),.clock(clock),.reset(reset),.samples_0(samples_0),.samples_1(samples_1),.samples_2(samples_2),.samples_3(samples_3),.samples_4(samples_4),.samples_5(samples_5),.samples_6(samples_6),.samples_7(samples_7),.samples_8(samples_8);caculatorU2

45、(.samples_0(samples_0),.samples_1(samples_1),.samples_2(samples_2),.samples_3(samples_3),.samples_4(samples_4),.samples_5(samples_5),.samples_6(samples_6),.samples_7(samples_7),.samples_8(samples_8),.Data_out(Data_out);endmodule,7/3/2020,35,MicroelectronicsSchoolXidianUniversity,elsebeginsamples_0=D

46、ata_in;samples_1=samples_0;samples_2=samples_1;samples_3=samples_2;samples_4=samples_3;samples_5=samples_4;samples_6=samples_5;samples_7=samples_6;samples_8=samples_7;endendendmodule,moduleshift_register(Data_in,clock,reset,samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,samples_6,sample

47、s_7,samples_8);input3:0Data_in;inputclock,reset;output3:0samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,samples_6,samples_7,samples_8;reg3:0samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,samples_6,samples_7,samples_8;always(posedgeclockornegedgereset)beginif(reset)beginsamp

48、les_0=4b0;samples_1=4b0;samples_2=4b0;samples_3=4b0;samples_4=4b0;samples_5=4b0;samples_6=4b0;samples_7=4b0;samples_8=4b0;end,7/3/2020,36,MicroelectronicsSchoolXidianUniversity,modulecaculator(samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,samples_6,samples_7,samples_8,Data_out);input3:

49、0samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,samples_6,samples_7,samples_8;output9:0Data_out;wire9:0Data_out;wire3:0out_tmp_1,out_tmp_2,out_tmp_3,out_tmp_4,out_tmp_5;wire7:0out1,out2,out3,out4,out5;parameterb0=4b0010;parameterb1=4b0011;parameterb2=4b0110;parameterb3=4b1010;parameterb

50、4=4b1100;mul_addtreeU1(.mul_a(b0),.mul_b(out_tmp_1),.mul_out(out1);mul_addtreeU2(.mul_a(b1),.mul_b(out_tmp_2),.mul_out(out2);mul_addtreeU3(.mul_a(b2),.mul_b(out_tmp_3),.mul_out(out3);mul_addtreeU4(.mul_a(b3),.mul_b(out_tmp_4),.mul_out(out4);mul_addtreeU5(.mul_a(b4),.mul_b(samples_4),.mul_out(out5);a

51、ssignout_tmp_1=samples_0+samples_8;assignout_tmp_2=samples_1+samples_7;assignout_tmp_3=samples_2+samples_6;assignout_tmp_4=samples_3+samples_5;assignData_out=out1+out2+out3+out4+out5;endmodule,7/3/2020,37,MicroelectronicsSchoolXidianUniversity,modulemul_addtree(mul_a,mul_b,mul_out);input3:0mul_a,mul

52、_b;/IOdeclarationoutput7:0mul_out;wire7:0mul_out;/Wiredeclarationwire7:0stored0,stored1,stored2,stored3;wire7:0add01,add23;assignstored3=mul_b3?1b0,mul_a,3b0:8b0;/Logicdesignassignstored2=mul_b2?2b0,mul_a,2b0:8b0;assignstored1=mul_b1?3b0,mul_a,1b0:8b0;assignstored0=mul_b0?4b0,mul_a:8b0;assignadd01=s

53、tored1+stored0;assignadd23=stored3+stored2;assignmul_out=add01+add23;endmodule,7/3/2020,38,MicroelectronicsSchoolXidianUniversity,moduleFIR_tb;regclock,reset;reg3:0Data_in;wire9:0Data_out;FIRU1(.Data_out(Data_out),.Data_in(Data_in),.clock(clock),.reset(reset);initialbeginData_in=0;clock=0;reset=1;#1

54、0reset=0;endalwaysbegin#5clock=clock;#5Data_in=Data_in+1;endendmodule,10.7.2Matlab生成滤波器,7/3/2020,39,MicroelectronicsSchoolXidianUniversity,matlab生成30阶低通1MHz海明窗函数设计步骤：,7/3/2020,40,MicroelectronicsSchoolXidianUniversity,图10.7-3海明窗函数设计,7/3/2020,41,MicroelectronicsSchoolXidianUniversity,图10.7-4滤波器量化设置,7

55、/3/2020,42,MicroelectronicsSchoolXidianUniversity,设置完成后，点击Targets中GenerateHDL，选择生成Verilog代码，设置路径，Matlab即可生成设计好的滤波器VerilogHDL代码以及测试文件，测试结果如图10.7-5所示。,10.8总线控制器设计,7/3/2020,43,MicroelectronicsSchoolXidianUniversity,10.8.1UART接口控制器,表10.8-1RS-232接口信号定义,7/3/2020,44,MicroelectronicsSchoolXidianUniversity,7

56、/3/2020,45,MicroelectronicsSchoolXidianUniversity,moduleUART_transmitter(clk,reset,byte_ready,data,TXD);inputclk,reset;inputbyte_ready;/loaddatacontrolinput7:0data;outputTXD;/serialdatareg9:0shift_reg;assignTXD=shift_reg0;always(posedgeclkornegedgereset)beginif(!reset)shift_reg=10b1111111111;elseif(

57、byte_ready)shift_reg=1b1,data,1b0;/addstartandstopbitelseshift_reg=1b1,shift_reg9:1;/outputserialdataendendmodule,7/3/2020,46,MicroelectronicsSchoolXidianUniversity,moduleUART_receiver(clk,reset,RXD,data_out);parameteridle=2b00;parameterreceiving=2b01;inputclk,reset;inputRXD;/serialdataoutput7:0data

58、_out;regshift;/shiftcontrolreginc_count;/increasecountercontrolreg7:0data_out;reg7:0shift_reg;reg3:0count;reg2:0state,next_state;always(stateorRXDorcount)beginshift=0;inc_count=0;next_state=state;case(state),idle:if(!RXD)next_state=receiving;/checkthestartbitreceiving:beginif(count=8)begindata_out=shift_reg;/outputdatanext_state=idle