ADC串行读取和设计要点

1、SAR型ADC串行读取和设计要点,叶健 Sept. 2013,2,SAR型ADC的CONV信号,3,SAR型ADC的CONV信号,4,Reading after a conversion and reading during a conversion,5,Understand the timing specifications pre-condition,6,Understand the timing specifications pre-condition,7,e.g. Simple calculation of max sampling rate when reading after a

2、conversion by SPI mode,Assume no OS, Vdrive = 2.7V, 0.3Vdrive0.7Vdrive as logic input level tconv = 4.15us (max) t1 = 45ns (max); t2 = 25ns (min) fsclk = 12.5MHz (min) = 8X16 clock = 10.24us A total time of tcycle = 4.15us + 45ns + 25ns + 10.24us = 14.45us Take 0.05us as the design buffer = 15.5us F

3、sample (max) = 64.5ksps,8,Question,Datasheet 上的9.4us哪里来的，你刚才算下来明明是14. 5us么？！,9,A real case: why my ADC value is only half?,MCU,AD7606,AD7606,AD7606,AD7606,SCLK,A real case: how to calculate the data delay after sclk from low to high?,FPGA IP Core,clock signal IO delay,clock trace delay,ADC “t19”,dat

4、a trace delay,data IO delay,T total delay,11,When isolated, things getting more worse,FPGA,SCLK,SDO,ADUM1401,tpd = 1 ns,tpd = 1 ns,t = 3 ns,t = 4 ns,tpd = 45 ns,t = 49 ns,t = 50 ns,tco = 11 ns,tpd = 1 ns,tpd = 45 ns,tpd = 1 ns,t = 61 ns,t = 62 ns,t = 107 ns,t = 108 ns,Osc,SCLK,SDO,tsu = 3 ns,t = 111

5、 ns,12,Customer Isolation issue with AD7980Workaround,SCLK Loopback,A real case by single ground ADC,Common interfacing mode to PulSARs eg. AD7980 3 wire mode Continuous SCLK operation on BF SPORT, (+ many processors) Sensitivity to activity on SCLK during sensitive bit trials CMOS inputs, large sig

6、nal swing and ground bounce Only 1 GND pin on these parts Performance degradation 1dB SNR with continuous SCLK at 16 bit level Simplest solution is to gate the SCLK externally with CS,Performance to 18 bits, Burst vs Continuous SCLK,SPORT vs SPI BF527,SPORT Hardware interface low Jitter Continuous S

7、CLK DMA possible Faster SCLK rates 60MHz Any number of SCLKs in frame SPI Limited HW CS implementations, when SW based interface - More jitter on CS SCLK is framed with CS Slower SCLK rates 30MHz SCLKs are in multiples of 8,Sampling Clock Jitter and Aperture Jitter Increase ADC Noise,TOTAL JITTER =

8、t j (RMS),TOTAL JITTER =,(ADC APERTURE JITTER) 2 + (SAMPLING CLOCK JITTER) 2,SNR Due to Aperture and Sampling Clock Jitter,tj = 1ps,tj = 10ps,tj = 100ps,tj = 1ns,fin/Hz,SNR/dB,Clocking AD7626,Standard eval board CED1Z uses FPGA generated CNV input FPGAs do not specify jitter, SNR performance degrades as input tone is increased New development on SDP-H u