CMOS大规模集成电路.ppt

1、Introduction toCMOS VLSIDesignLecture 4: DC & Transient Response,4: DC and Transient Response,Slide 2,Outline,DC Response Logic Levels and Noise Margins Transient Response Delay Estimation,4: DC and Transient Response,Slide 3,Activity,1) If the width of a transistor increases, the current will incre

2、asedecreasenot change 2) If the length of a transistor increases, the current will increasedecreasenot change 3) If the supply voltage of a chip increases, the maximum transistor current will increasedecreasenot change 4) If the width of a transistor increases, its gate capacitance will increasedecr

3、easenot change 5) If the length of a transistor increases, its gate capacitance will increasedecreasenot change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increasedecreasenot change,4: DC and Transient Response,Slide 4,Activity,1) If the width of a tra

4、nsistor increases, the current will increasedecreasenot change 2) If the length of a transistor increases, the current will increasedecreasenot change 3) If the supply voltage of a chip increases, the maximum transistor current will increasedecreasenot change 4) If the width of a transistor increase

5、s, its gate capacitance will increasedecreasenot change 5) If the length of a transistor increases, its gate capacitance will increasedecreasenot change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increasedecreasenot change,4: DC and Transient Response,

6、Slide 5,DC Response,DC Response: Vout vs. Vin for a gate Ex: Inverter When Vin = 0 - Vout = VDD When Vin = VDD - Vout = 0 In between, Vout depends on transistor size and current By KCL, must settle such that Idsn = |Idsp| We could solve equations But graphical solution gives more insight,4: DC and T

7、ransient Response,Slide 6,Transistor Operation,Current depends on region of transistor behavior For what Vin and Vout are nMOS and pMOS in Cutoff? Linear? Saturation?,4: DC and Transient Response,Slide 7,nMOS Operation,4: DC and Transient Response,Slide 8,nMOS Operation,4: DC and Transient Response,

8、Slide 9,nMOS Operation,Vgsn = Vin Vdsn = Vout,4: DC and Transient Response,Slide 10,nMOS Operation,Vgsn = Vin Vdsn = Vout,4: DC and Transient Response,Slide 11,pMOS Operation,4: DC and Transient Response,Slide 12,pMOS Operation,4: DC and Transient Response,Slide 13,pMOS Operation,Vgsp = Vin - VDD Vd

9、sp = Vout - VDD,Vtp 0,4: DC and Transient Response,Slide 14,pMOS Operation,Vgsp = Vin - VDD Vdsp = Vout - VDD,Vtp 0,4: DC and Transient Response,Slide 15,I-V Characteristics,Make pMOS is wider than nMOS such that bn = bp,4: DC and Transient Response,Slide 16,Current vs. Vout, Vin,4: DC and Transient

10、 Response,Slide 17,Load Line Analysis,For a given Vin: Plot Idsn, Idsp vs. Vout Vout must be where |currents| are equal in,4: DC and Transient Response,Slide 18,Load Line Analysis,Vin = 0,4: DC and Transient Response,Slide 19,Load Line Analysis,Vin = 0.2VDD,4: DC and Transient Response,Slide 20,Load

11、 Line Analysis,Vin = 0.4VDD,4: DC and Transient Response,Slide 21,Load Line Analysis,Vin = 0.6VDD,4: DC and Transient Response,Slide 22,Load Line Analysis,Vin = 0.8VDD,4: DC and Transient Response,Slide 23,Load Line Analysis,Vin = VDD,4: DC and Transient Response,Slide 24,Load Line Summary,4: DC and

12、 Transient Response,Slide 25,DC Transfer Curve,Transcribe points onto Vin vs. Vout plot,4: DC and Transient Response,Slide 26,Operating Regions,Revisit transistor operating regions,4: DC and Transient Response,Slide 27,Operating Regions,4: DC and Transient Response,Slide 28,Beta Ratio,If bp / bn 1,

13、switching point will move from VDD/2 Called skewed gate HI-skew inverter: if Vin = VDD/2, Vout VDD/2 so the input threshold VDD/2,4: DC and Transient Response,Slide 29,Noise Margins,How much noise can a gate input see before it does not recognize the input?,4: DC and Transient Response,Slide 30,Nois

14、e Margins,How much noise can a gate input see before it does not recognize the input? NML = VIL VOL NMH = VOH VIH,4: DC and Transient Response,Slide 31,Logic Levels,To maximize noise margins, select logic levels at,4: DC and Transient Response,Slide 32,Logic Levels,To maximize noise margins, select

15、logic levels at unity gain point of DC transfer characteristic,4: DC and Transient Response,Slide 33,Transient Response,DC analysis tells us Vout if Vin is constant Transient analysis tells us Vout(t) if Vin(t) changes Requires solving differential equations Input is usually considered to be a step

16、or ramp From 0 to VDD or vice versa,4: DC and Transient Response,Slide 34,Inverter Step Response,Ex: find step response of inverter driving load cap,4: DC and Transient Response,Slide 35,Inverter Step Response,Ex: find step response of inverter driving load cap,4: DC and Transient Response,Slide 36,

17、Inverter Step Response,Ex: find step response of inverter driving load cap,4: DC and Transient Response,Slide 37,Inverter Step Response,Ex: find step response of inverter driving load cap,4: DC and Transient Response,Slide 38,Inverter Step Response,Ex: find step response of inverter driving load cap

18、,4: DC and Transient Response,Slide 39,Inverter Step Response,Ex: find step response of inverter driving load cap,4: DC and Transient Response,Slide 40,Delay Definitions,tpdr: tpdf: tpd: tr: tf: fall time,4: DC and Transient Response,Slide 41,Delay Definitions,tpdr: rising propagation delay (worst-c

19、ase) Max time from input to rising output crossing VDD/2 tpdf: falling propagation delay (worst-case) Max time from input to falling output crossing VDD/2 tpd: average propagation delay tpd = (tpdr + tpdf)/2 tr: rise time Rise from 0.2 VDD to 0.8 VDD of its steady-state value tf: fall time Fall from

20、 0.8 VDD to 0.2 VDD of its steady-state value,4: DC and Transient Response,Slide 42,Delay Definitions,tcdr: rising contamination delay (best-case) Min time from input to rising output crossing VDD/2 tcdf: falling contamination delay (best-case) Min time from input to falling output crossing VDD/2 tc

21、d: average contamination delay tpd = (tcdr + tcdf)/2,4: DC and Transient Response,Slide 43,Simulated Inverter Delay,Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate I-V models too! But simulations take time to write,4: DC and Tran

22、sient Response,Slide 44,Delay Estimation,We would like to be able to easily estimate delay Not as accurate as simulation But easier to ask “What if?” The step response usually looks like a 1st order RC response with a decaying exponential. Use RC delay models to estimate delay C = total capacitance

23、on output node Use effective resistance R So that tpd = RC Characterize transistors by finding their effective R Depends on average current as gate switches,4: DC and Transient Response,Slide 45,RC Delay Models,Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance

24、Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width,4: DC and Transient Response,Slide 46,Example: 3-input NAND,Sketch a 3-input NAND with transistor widths chosen to achieve effective rise

25、and fall resistances equal to a unit inverter (R).,4: DC and Transient Response,Slide 47,Example: 3-input NAND,Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).,4: DC and Transient Response,Slide 48,Example: 3-input NAND,

26、Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).,4: DC and Transient Response,Slide 49,3-input NAND Caps,Annotate the 3-input NAND gate with gate and diffusion capacitance.,4: DC and Transient Response,Slide 50,3-input N

27、AND Caps,Annotate the 3-input NAND gate with gate and diffusion capacitance.,4: DC and Transient Response,Slide 51,3-input NAND Caps,Annotate the 3-input NAND gate with gate and diffusion capacitance.,Shared source and drain,4: DC and Transient Response,Slide 52,Elmore Delay,ON transistors look like

28、 resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder,4: DC and Transient Response,Slide 53,Example: 2-input NAND,Estimate worst-case rising and falling delay of 2-input NAND driving h identical gates.,4: DC and Transient Response,Slide 54,Example: 2-input NAND,Estimat

29、e rising and falling propagation delays of a 2-input NAND driving h identical gates.,4: DC and Transient Response,Slide 55,Example: 2-input NAND,Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.,4: DC and Transient Response,Slide 56,Example: 2-input NAND,Est

30、imate rising and falling propagation delays of a 2-input NAND driving h identical gates.,4: DC and Transient Response,Slide 57,Example: 2-input NAND,Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.,4: DC and Transient Response,Slide 58,Example: 2-input NAND,Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.,4: DC and Tr