03_其它资料cost-optimized-product-selection-guide_W

1、 Copyright 20152016 Xilinx Spartan- FPGAsSpartan-6 LX FPGAsI/O Optimization at the Lowest Cost (1.2V, 1.0V)Spartan-6 LXT FPGAsI/O Optimization at the Lowest-Cost with Serial Connectivity (1.2V)Part NumberXC6SLX4XC6SLX9XC6SLX16XC6SLX25XC6SLX45XC6SLX75XC6SLX100XC6SLX150XC6SLX25TXC6SLX45TXC6SLX75TXC6SL

2、X100TXC6SLX150TSlices(1)6001,4302,2783,7586,82211,66215,82223,0383,7586,82211,66215,82223,038Logic Cells(2)3,8409,15214,57924,05143,66174,637101,261147,44324,05143,66174,637101,261147,443CLB Flip-Flops4,80011,44018,22430,06454,57693,296126,576184,30430,06454,57693,296126,576184,304Max. Distributed R

3、AM (Kb)75901362294016929761,3552294016929761,355Block RAM (18Kb each)1232325211617226826852116172268268Total Block RAM (Kb)(3)2165765769362,0883,0964,8244,8249362,0883,0964,8244,824Clock Mgmt Tiles (CMT)(4)2222466624666Max. Single-Ended I/O Pins132200232266358408480576250296348498540Max. Differentia

4、l I/O Pairs66100116133179204240288125148174249270DSP48A1 Slices(5)8163238581321801803858132180180Endpoint Block for PCIe11111Memory Controller Blocks0222244422444GTP Low-Power Transceivers24888Commercial Speed Grade(10)-1L, -2, -3-1L, -2, -3, -3N-1L, -2, -3, -3N-1L, -2, -3, -3N-1L, -2, -3, -3N-1L, -

5、2, -3, -3N-1L, -2, -3, -3N-1L, -2, -3, -3N-2, -3, -3N-2, -3, -3N-2, -3, -3N-2, -3, -3N-2, -3, -3NIndustrial Speed Grade(10)-1L, -2, -3-1L, -2, -3, -3N-1L, -2, -3, -3N-1L, -2, -3, -3N-1L, -2, -3, -3N-1L, -2, -3, -3N-1L, -2, -3, -3N-1L, -2, -3, -3N-2, -3, -3N-2, -3, -3N-2, -3, -3N-2, -3, -3N-2, -3, -3

6、NConfiguration Memory (Mb)6.411.919.626.533.86.411.919.626.533.8BodyBallArea Pitch Package(mm) (mm)Maximum User I/O: SelectIO InterfacePins (GTP Transceivers)(6)CPG196(7)TQG144(7) CSG225(8)8 x 820 x 2013 x 106106106102102132160160CSG324 CSG484(9) FT(G)256 FG(G)484(9)FG(G)67615 x

7、1.01.0200232226218190 (2)190 (4) 19 x 19 17 x 17 23 x 23 27 x 27 320328338338296 (4)292 (4)296 (4)296 (4)186186186266316280326338250 (2)296 (4)268 (4)296 (4)296 (4)358408480498348 (8)376 (8)396 (8)FG(G)90031 x 311.0576498 (8)540 (8)Page 3 Copyright 20152016 XilinxNotes:1. Each slice conta

8、ins four LUTs and eight flip-flops.2. Spartan-6 FPGA logic cell ratings reflect the increased logic capacity offered by the 6-input LUT architecture.3. Block RAM are fundamentally 18Kb in size. Each block can also be used as two independent 9 Kb blocks.4. Each CMT contains two DCMs and one PLL.5. Ea

9、ch DSP48A1 slice contains an 18x18 multiplier, an adder, and an accumulator.6. The LX device pinouts are not compatible with the LXT device pinouts.7. CPG196 and TQG144 do not have memory controller support. -3N is not available for these packages.8. CSG225 has X8 memory controller support in the LX

10、9 and LX16 devices. There is no memory controller in the LX4 devices.9. Devices in the FG(G)484 and CSG484 packages have support for two memory controllers.10. Devices with -3N speed grade do not support MCB functionality.Spartan-7 FPGAsI/O Optimization at the Lowest Cost and Highest Performance-per

11、-WattPart NumberXC7S6XC7S15XC7S25XC7S50XC7S75XC7S100Logic Cells6,00012,80023,36052,16076,800102,400Slices9382,0003,6508,15112,00016,000CLB Flip-Flops7,50016,00029,20065,20096,000128,000Max. Distributed RAM (Kb)701503136008321,100Block RAM/FIFO w/ ECC (36 Kb each)510457590120Total Block RAM (Kb)18036

12、01,6202,7003,2404,320Clock Mgmt Tiles (1 MMCM + 1 PLL)223588Max. Single-Ended I/O Pins100100150250400400Max. Differential I/O Pairs484872120192192DSP Slices102080120140160Analog Mixed Signal (AMS) / XADC001111Configuration AES / HMAC Blocks001111Commercial Speed Grade-1,-2-1,-2-1,-2-1,-2-1,-2-1,-2In

13、dustrial Speed Grade-1,-2,-1L-1,-2,-1L-1,-2,-1L-1,-2,-1L-1,-2,-1L-1,-2,-1LPackage(1)Body Area (mm)Available User I/O: 3.3V SelectIO HR I/OCPGA1968x88686CSGA22513SGA32415x15150210TQGA14420x20727260FGGA48423x23250338338FGGA67627x27400400Notes:1. Packages with the same last letter and numb

14、er sequence, e.g., A484, are footprint compatible with all other Spartan-7 devices with the same sequence. The footprint compatible devices within this family are outlined. Artix-7 FPGAsArtix-7 FPGAsTransceiver Optimization at the Lowest Cost and Highest DSP Bandwidth (1.0V, 0.95V, 0.9V)Part NumberX

15、C7A12TXC7A15TXC7A25TXC7A35TXC7A50TXC7A75TXC7A100TXC7A200TLogic ResourcesLogic Cells12,80016,64023,36033,28052,16075,520101,440215,360Slices2,0002,6003,6505,2008,15011,80015,85033,650CLB Flip-Flops16,00020,80029,20041,60065,20094,400126,800269,200Memory ResourcesMaximum Distributed RAM (Kb)1712003134

16、006008921,1882,888Block RAM/FIFO w/ ECC (36 Kb each)2025455075105135365Total Block RAM (Kb)7209001,6201,8002,7003,7804,86013,140Clock ResourcesCMTs (1 MMCM + 1 PLL)353556610I/O ResourcesMaximum Single-Ended I/O150250150250250300300500Maximum Differential I/O Pairs7212072120120144144240DSP Slices4045

17、8090120180240740EmbeddedPCIe Gen2(1)11111111Analog Mixed Signal (AMS) / XADC11111111Hard IPResourcesConfiguration AES / HMAC Blocks11111111GTP Transceivers (6.6 Gb/s Max Rate)(2)244448816Commercial-1, -2-1, -2-1, -2-1, -2-1, -2-1, -2-1, -2-1, -2Speed GradesExtended-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3

18、-2L, -3-2L, -3-2L, -3Industrial-1, -2, -1L-1, -2, -1L-1, -2, -1L-1, -2, -1L-1, -2, -1L-1, -2, -1L-1, -2, -1L-1, -2, -1LPackage(3), (4)Dimensions Ball Pitch(mm)(mm)Available User I/O: 3.3V SelectIO HRI/O (GTP Transceivers)CPG23610 x 100.5106 (2)106 (2)106 (4)106 (2)106 (2)CSG32415 x 150.8210 (0)210 (

19、0)210 (0)210 (0)210 (0)CSG32515 x 150.8150 (2)150 (4)150 (4)150 (4)150 (4)FTG25617 x 171.0170 (0)170 (0)170 (0)170 (0)170 (0)SBG484 / SBV48419 x 190.8285 (4)Footprint CompatibleFGG48423 x 231.0250 (4)250 (4)250 (4)285 (4)285 (4)FBG484 / FBV48423 x 231.0285 (4)Footprint CompatibleFGG67627 x 271.0300

20、(8)300 (8)FBG676 / FBV67627 x 271.0400 (8)FFG1156 / FFV115635 x 351.0500 (16)Notes: 1. Supports PCI Express Base 2.1 specification at Gen1 and Gen2 data rates.2. Represents the maximum number of transceivers available. Note that the majority of devices are available without transceivers. See the Pac

21、kage section of this table for details.3. Leaded package option available for all packages. See DS180, 7 Series FPGAs Overview for details.4. Device migration is available within the Artix-7 family for like packages but is not supported between other 7 series families.Page 4 Copyright 20152016 Xilin

22、x Zynq-7000 AP SoC FamilyCost-Optimized DevicesMid-Range DevicesDevice NameZ-7007SZ-7012SZ-7014SZ-7010Z-7015Z-7020Z-7030Z-7035Z-7045Z-7100Part NumberXC7Z007SXC7Z012SXC7Z014SXC7Z010XC7Z015XC7Z020XC7Z030XC7Z035XC7Z045XC7Z100Processing System (PS)Processor CoreSingle-CoreARM Cortex-A9 MPCoreUp to 766MH

23、zDual-CoreARM Cortex-A9 MPCore Up to 866MHzDual-CoreARM Cortex-A9 MPCore Up to 1GHz(1)Processor ExtensionsNEON SIMD Engine and Single/Double Precision Floating Point Unit per processorL1 Cache32KB Instruction, 32KB Data per processorL2 Cache512KBOn-Chip Memory256KBExternal Memory Support(2)DDR3, DDR

24、3L, DDR2, LPDDR2External Static Memory Support(2)2x Quad-SPI, NAND, NORDMA Channels8 (4 dedicated to PL)Peripherals2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIOPeripherals w/ built-in DMA(2)2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIOSecurity(3)RSA Authentication of First Stage Boo

25、t Loader,AES and SHA 256b Decryption and Authentication for Secure BootProcessing System to Programmable Logic Interface Ports (Primary Interfaces & Interrupts Only)2x AXI 32b Master, 2x AXI 32b Slave 4x AXI 64b/32b MemoryAXI 64b ACP16 Interrupts7 Series PL EquivalentArtix-7Artix-7Artix-7Artix-7Arti

26、x-7Artix-7Kintex-7Kintex-7Kintex-7Kintex-7ogrammable Logic (PL)Logic Cells23K55K65K28K74K85K125K275K350K444KLook-Up Tables (LUTs)14,40034,40040,60017,60046,20053,20078,600171,900218,600277,400Flip-Flops28,80068,80081,20035,20092,400106,400157,200343,800437,200554,800Total Block RAM (# 36Kb Blocks)1.

27、8Mb (50)2.5Mb (72)3.8Mb (107)2.1Mb (60)3.3Mb (95)4.9Mb (140)9.3Mb (265)17.6Mb (500)19.1Mb (545)26.5Mb (755)DSP Slices66120170801602204009009002,020PCI ExpressGen2 x4Gen2 x4Gen2 x4Gen2 x8Gen2 x8Gen2 x8Analog Mixed Signal (AMS) / XADC(2)2x 12 bit, MSPS ADCs with up to 17 Differential InputsSecurity(3)

28、AES & SHA 256b Decryption & Authentication for Secure Programmable Logic ConfigPrSpeed GradesCommercial-1-1-1-1Extended-2-2,-3-2,-3-2Industrial-1, -2-1, -2, -1L-1, -2, -2L-1, -2, -2LNotes:1. 1 GHz processor frequency is available only for -3 speed grades for devices in flip-chip packages. Please see

29、 the data sheet for more details.2. Z-7007S and Z-7010 in CLG225 have restrictions on PS peripherals, memory interfaces, and I/Os. Please refer to the Technical Reference Manual for more details.3. Security block is shared by the Processing System and the Programmable Logic.Page 5 Copyright 20152016

30、 XilinxHR I/O, HP I/O, PS I/O, and Transceivers (GTP or GTX)Cost-Optimized DevicesMid-Range DevicesDevice NameZ-7007SZ-7012SZ-7014SZ-7010Z-7015Z-7020Z-7030Z-7035Z-7045Z-7100Package FootprintDimensions (mm) (1)HR I/O, HP I/OPS I/O(2), GTP TransceiversHR I/O, HP I/OPS I/O(2), GTX TransceiversCLG22513x

31、1354, 084(3), 054, 084(3), 0CLG40017x17100, 0128, 0125, 0128, 0100, 0128, 0125, 0128, 0CLG48419x19200, 0128, 0200, 0128, 0CLG485(4)19x19150, 0128, 4150, 0128, 4SBG485 / SBV485(4)19x1950, 100128, 4FBG484 / FBV48423x23100, 63128, 4FBG676 / FBV676(1)27x27100, 150128, 4100, 150128, 8100, 150128, 8FFG676

32、 / FFV676(1)27x27100, 150128, 4100, 150128, 8100, 150128, 8FFG900 / FFV90031x31212, 150128, 16212, 150128, 16212, 150128, 16FFG1156 / FFV115635x35250, 150128, 16Notes:1. Devices in the same package are footprint compatible. FBG676 / FBV676 and FFG676 / FFV676 are also footprint compatible.2. PS I/O

33、count does not include dedicated DDR calibration pins.3. PS DDR and PS MIO pin count is limited by package size. See DS190, Zynq-7000 All Programmable SoC Overview for details.4. CLG485 and SBG485 / SBV485 are pin-to-pin compatible. See product data sheets and user guides for more details. See DS190

34、, Zynq-7000 All Programmable SoC Overview for package details.Page 6 Copyright 20152016 Xilinx Spartan-6 FPGA Speed GradesDevice Name(1)Speed GradeXC6SLX4XC6SLX9XC6SLX16XC6SLX25XC6SLX45XC6SLX75XC6SLX100XC6SLX150XC6SLX25TXC6SLX45TXC6SLX75TXC6SLX100TXC6SLX150T-1L-2-3-3N-1L -2-3-3NPage 7 Copyright 2015

35、2016 XilinxCINotes:1. For full part number details, see the Ordering Information section in DS160, Spartan-6 Family Overview. Available Not offeredC = Commercial (Tj = 0C to +85C) I = Industrial (Tj = 40C to +100C) Spartan-7 FPGA Speed GradesDevice Name(1)Speed GradeXC7S6XC7S15XC7S25XC7S50XC7S75XC7S

36、100-1-2-1-2-1LPage 8 Copyright 20152016 XilinxCINotes:1. For full part number details, see the Ordering Information section in DS180, 7 Series FPGAs Overview. Available Not offeredC = Commercial (Tj = 0C to +85C) I = Industrial (Tj = 40C to +100C) Artix-7 FPGA Speed GradesDevice Name(1)CEISpeed Grad

37、eXC7A12TXC7A15TXC7A25TXC7A35TXC7A50TXC7A75TXC7A100TXC7A200T-1-2-2L-3-1-1L-2Page 9 Copyright 20152016 XilinxNotes:1. For full part number details, see the Ordering Information section in DS180, 7 Series FPGAs Overview. Available Not offeredC = Commercial (Tj = 0C to +85C) E = Extended (Tj = 0C to +10

38、0C) I = Industrial (Tj = 40C to +100C) Zynq-7000 Family Speed GradesDevice Name(1)Speed GradeZ-7007SZ-7012SZ-7014SZ-7010Z-7015Z-7020Z-7030Z-7035Z-7045Z-7100-1-2-3-1-2-1L-2LPage 10 Copyright 20152016 XilinxC EINotes:1. For full part number details, see the Ordering Information section in DS190, Zynq-

39、7000 All Programmable SoC Overview. Available Not offeredC = Commercial (Tj = 0C to +85C) E = Extended (Tj = 0C to +100C) I = Industrial (Tj = 40C to +100C)Page 11 Copyright 20152016 XilinxDevice Ordering InformationXC6SLX LXTFootprint#-1FBG900CXilinx CommercialGenerationFamilySub-familiesLogic Cell

40、sIn 1K unitsSpeed Grade-L1 = Low PowerPackage TypeCP: Wire-bond (.5mm)G: RoHS 6/6Package Pin CountTemperature Grade-2 = Mid-3 = HighestTQ: Quad Flat Pack (.5mm) CS: Wire-bond (.8mm)FT: Wire-bond (1mm) FG: Wire-bond (1mm)Footprint(C, E, I)XC7S#-1FGGA484CXilinx CommercialGenerationFamilyLogic Cells In

41、 1K unitsSpeed Grade-1 = Slowest-L1 = Low Power-2 = MidPackage TypeCP: Wire-bond (.5mm)TQ: Quad Flat Pack (.5mm) CS: Wire-bond (.8mm)FG: Wire-bond (1mm)G: RoHS 6/6Package DesignatorPackagePin CountTemperature Grade (C, I)FootprintXC7A#-1FFV900CXilinx CommercialGenerationFamilyLogic Cells In 1K units

42、Speed Grade-1 = Slowest-L1 = Low Power-L2 = Low Power-2 = Mid-3 = HighestPackage TypeCP: Wire-bond (.5mm) CS: Wire-bond (.8mm)SB: Flip-chip Lidless (.8mm) FT: Wire-bond (1mm)FG: Wire-bond (1mm)FB: Flip-chip Lidless (1mm) FF: Flip-chip (1mm)V: RoHS 6/6 G: RoHS 6/6w/exemption 15FootprintNominal Packag

43、e Pin CountTemperature Grade(C, E, I)XC7Z#S-1FFV#CXilinx CommercialGenerationFamilyValue IndexSingle CoreIndicator (Z-7007S,Speed Grade-1: Slowest-L1: Low PowerPackage Type CL: Wire-bond (.8mm)V: RoHS 6/6G (CLG) = RoHS 6/6 G (SBG, FBG, FFG) =Package Pin CountTemperature Grade(C, E, I)Notes:-L1 is th

44、e ordering code for the lower power, -1L speed grade.-L2 is the ordering code for the lower power, -2L speed grade.C = Commercial (Tj = 0C to +85C) E = Extended (Tj = 0C to +100C) I = Industrial (Tj = 40C to +100C)Z-7012S, Z-7014S)-2: Mid-L2: Low Power-3: FastestSB: Flip-chip Lidless (.8mm)FB: Flip-

45、chip Lidless (1mm)FF: Flip-chip Lidded (1mm)RoHS 6/6 with exemption 15Important: Verify all data in this documentwith the device data sheets found at Spartan-6 Device Footprint Compatibility8mm31mmI/O, GTP TransceiversDimensions (mm)8x813x1315x1517x1719x1920x2023x2327x2731x31Unique FootprintCPG196CSG225CSG324FTG256CSG484TQG144FGG484FGG676FGG900XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX45 XC6SLX75 XC6SLX100XC6SLX150106, 0106, 0106, 0132, 0160, 0160, 0102, 0102, 0200, 0232, 0226, 0218, 0186, 0186, 0186, 0266, 0316, 0280, 0326, 0338, 0320, 0328, 0338, 03