数字钟实验报告

1、华中科技大学电子线路设计、测试与实验实验报告实验名称：多功能数字钟设计院（系）：自动化学院专业班级：实验成绩：指导教师：汪小燕2014 年6 月 11 日一、实验目的1. 掌握可编程逻辑器件的应用开发技术，设计输入、编译、仿真和器件编程；2. 熟悉EDA软件使用；3. 掌握Verilog HDL设计方法； 4. 分模块、分层次数字系统设计 二、实验器材QUARTUS II软件 PC DEO实验板三、实验要求1. 能显示小时、分钟、秒钟（小时以24进制,时、分用显示器，秒用 LED）2. 能调整小时、分钟的时间3. 复位四、实验原理五、程序设计过程数字钟由2个60进制计数器和1个24进制计数器和

2、4个译码器共7个模块构成,3个计数器公用一个时钟信号CP。2个选择器分别用于选择分计数器和时计数器的使能控制信号,对时间进行校正时,在控制器的作用下,使能信号接高电平,此时每来一个时钟信号,计数器加一计数,从而实现对小时和分钟的校正.正常计时时,使能信号来自低位计数器的输出,即秒计数器达到59秒时,产生输出信号使分计数器加1,分秒计数器同时计到最大值时即59分59秒时,产生输出信号使小时计数器加一。1.顶层模块：module clock (led0, led1, led2, led3, led_sec, _50mhzin, adjminkey, adjhrkey, ncr, h12, hour

3、12);input _50mhzin;input adjminkey, adjhrkey;input h12;input ncr;output 6:0led0, led1, led2, led3;wire 7:0 led_a, led_b;wire _1hz, _1khz, _5hz;wire 7:0 hour, minute, second, set_hr, set_min; output hour12;wire h12;output 7:0led_sec;assign hour12 = h12; divided_frequency u0(_1hz,ncr,_50mhzin);top_clo

4、ck u1(hour, minute, second, _1hz, ncr, adjminkey, adjhrkey, _50mhzin);display u2(_50mhzin, _5hz, ncr, led_a, led_b, led_sec, hour, minute, second, h12);SEG7_LUT u3(led_a7:4, led3);SEG7_LUT u4(led_a3:0, led2);SEG7_LUT u5(led_b7:4, led1);SEG7_LUT u6(led_b3:0, led0); endmodule2.分频模块：module divided_freq

5、uency(_1hzout,ncr,_50mhzin);input _50mhzin, ncr;output _1hzout;supply1 vdd;wire11:0 q;wire _1khzin;wire en1, en2;divfreq50M_1Khz du00(_1khzin, ncr, _50mhzin);/先调用1khz分频counter10 du0(q3:0, ncr, vdd, _1khzin);counter10 du1(q7:4, ncr, en1, _1khzin);counter10 du2(q11:8, ncr, en2, _1khzin);/再调用三个10计数器,将1

6、khz分为1hzassign en1=(q3:0 = 4h9);assign en2=(q7:4 = 4h9) & (q3:0 = 4h9);assign _1hzout = q11;assign _500hzout = q0;endmodule3.时钟运行模块module top_clock(hour, minute, second, _1hz, ncr, adjminkey, adjhrkey, _50mhzin);input _1hz, _50mhzin, ncr, adjminkey, adjhrkey;output 7:0 hour, minute, second;wire 7:0

7、hour, minute, second;/时、分、秒每个用八位二进制表示两位BCD码supply1 vdd; /高电平，是使能一直打开wire mincp, hrcp, _5hz;/_5hz用于快速校时divfreq50M_5hz ut0(_5hz, ncr, _50mhzin);counter60 ut1(second, ncr, vdd, _1hz);counter60 ut2(minute, ncr, vdd, mincp);/秒和分使用60进制counter24 ut3(hour7:4, hour3:0, ncr, vdd, hrcp);/时钟为24进制（默认）assign minc

8、p = adjminkey ? _5hz : (second=8h59);assign hrcp = adjhrkey? _5hz : (minute,second=16h5959);/进位或校时使能控制endmodule4.显示模块：module display(_50mhz,_5hz,cr,led_a,led_b,led_sec,hour,minute,second,h12);input 7:0hour,minute,second;/时分秒input _50mhz,cr,_5hz;output 7:0led_a,led_b,led_sec;/数码管显示缓存input h12;/12,24小

9、时制切换reg 7:0led_a,led_b,led_sec;reg 2:0mod;/模式变量always(posedge _50mhz)beginled_b=minute;led_sec=second;/模式0,显示时分秒if(h12)begin led_a=hour;led_b=minute;led_sec=second;endelsebegincase(hour)8h13,8h14,8h15,8h16,8h17,8h18,8h19,8h22,8h23,8h24:led_a=hour-8h12;8h20:led_a=8h08;8h21:led_a=8h09;default:led_a=ho

10、ur;endcaseend/12/24小时切换,24到12,相应BCD码减endendmodule5.数码管操作模块module SEG7_LUT(iDIG,oSEG);input3:0iDIG;output6:0oSEG;reg6:0oSEG;always (iDIG)begincase(iDIG)4h1: oSEG = 7b; / -t-4h2: oSEG = 7b; / | |4h3: oSEG = 7b; / lt rt4h4: oSEG = 7b; / | |4h5: oSEG = 7b; / -m-4h6: oSEG = 7b; / | |4h7: oSEG = 7b; / lb

11、rb4h8: oSEG = 7b; / | |4h9: oSEG = 7b; / -b-4ha: oSEG = 7b;4hb: oSEG = 7b;4hc: oSEG = 7b;4hd: oSEG = 7b;4he: oSEG = 7b;4hf: oSEG = 7b;4h0: oSEG = 7b;endcaseendendmodule六、功能仿真1.六进制2.十进制3.六十进制（分了几张图截图）4.24进制5. 异步清零仿真6.正常计时仿真l 秒计时l 分计时l 小时计时l 23:59:59秒返07 手动校小时和分钟仿真ADJHrKey 与 AdjMinKey均为高电平有效，七、思考题1.什么

12、是分层次的电路设计方法?叙述分层次设计电路的基本过程.答: 在电路设计中,可以将两个或者多个模块组合起来描述电路逻辑功能,通常称为分层次的电路设计.自顶而下和自底而上是两种常用的设计方法.在自顶而下的设计中,先定义顶层模块,然后再定义顶层模块中用到的子模块.而在自底而上的设计中,底层的各个子模块首先被确定下来,然后将这些子模块组合起来构成顶层模块.2.在用MAX+PLUS II 软件设计数字钟电路时,简述对60进制计数器进行仿真分析的大致过程.若仿真时栅格的大小(GRID SIZE)为0.5ms,设置CP信号时倍率(Multiplied By)为软件默认值1,那么仿真文件的时间至少需要多长才能

13、完整反映计数过程?答: 至少要0.5ms * 60 = 30ms八、 试验中遇到的问题与解决办法这次实验主要是Verilog代码的编写和仿真，在波形的仿真过程中，有许多操作并不清楚，尤其是部分功能的波形仿真输出和如何手动调整时钟的波形仿真，虽然最后有同学帮忙，但是最后还是操作得很不熟练。九、 实验小结本次实验让我们巩固了Verilog代码编写与波形仿真，掌握了更多了相关波形的仿真操作，但是在部分功能的操作上，以及网格的重新建立等方面显得仍然不够熟练，还需要更多的锻炼。十、附录（附源代码）/clock.vmodule clock(led0,led1,led2,led3,led_sec,_50mh

14、zin,adjminkey,adjhrkey,ncr,h12,hour12);input _50mhzin;input adjminkey, adjhrkey;input h12;input ncr;output 6:0led0, led1, led2, led3;wire 7:0 led_a, led_b;wire _1hz, _1khz, _5hz;wire 7:0 hour, minute, second, set_hr, set_min; output hour12;wire h12;output 7:0led_sec;wire 3:0hour_num1, hour_num0, min

15、_num1, min_num0, second_num1, second_num0;assign hour12 = h12; divided_frequency u0(_1hz,ncr,_50mhzin);top_clock u1(hour, minute, second, _1hz, ncr, adjminkey, adjhrkey, _50mhzin);display u2(_50mhzin, _5hz, ncr, led_a, led_b, led_sec, hour, minute, second, h12);SEG7_LUT u3(led_a7:4, led3);SEG7_LUT u

16、4(led_a3:0, led2);SEG7_LUT u5(led_b7:4, led1);SEG7_LUT u6(led_b3:0, led0); Endmodule/topclock.vmodule top_clock(hour, minute, second, _1hz, ncr, adjminkey, adjhrkey, _50mhzin);input _1hz, _50mhzin, ncr, adjminkey, adjhrkey;output 7:0 hour, minute, second;output 3:0 hour_num1, hour_num0, min_num1, mi

17、n_num0, second_num1, second_num0;wire 7:0 hour, minute, second;/时、分、秒每个用八位二进制表示两位BCD码supply1 vdd; /高电平，是使能一直打开wire mincp, hrcp, _5hz;/_5hz用于快速校时wire 3:0 hour_num1, hour_num0, min_num1, min_num0, second_num1, second_num0;/divfreq50M_5hz ut0(_5hz, ncr, _50mhzin);counter60 ut1(second, ncr, vdd, _1hz);c

18、ounter60 ut2(minute, ncr, vdd, mincp);/秒和分使用60进制counter24 ut3(hour7:4, hour3:0, ncr, vdd, hrcp);/时钟为24进制（默认）assign mincp = adjminkey ? _5hz : (second=8h59);assign hrcp = adjhrkey? _5hz : (minute,second=16h5959);/进位或校时使能控制assign hour_num13:0 = hour7:4;assign hour_num0 = hour3:0;assign min_num1 = minu

19、te7:4;assign min_num1 = minute3:0;assign second_num1 = second7:4;assign second_num0 = second3:0;endmodule/display.vmodule display(_50mhz,_5hz,cr,led_a,led_b,led_sec,hour,minute,second,h12);input 7:0hour,minute,second;/时分秒input _50mhz,cr,_5hz;output 7:0led_a,led_b,led_sec;/数码管显示缓存input h12;/12,24小时制切

20、换reg 7:0led_a,led_b,led_sec;reg 2:0mod;/模式变量always(posedge _50mhz)beginled_b=minute;led_sec=second;/模式0,显示时分秒if(h12)begin led_a=hour;led_b=minute;led_sec=second;endelsebegincase(hour)8h13,8h14,8h15,8h16,8h17,8h18,8h19,8h22,8h23,8h24:led_a=hour-8h12;8h20:led_a=8h08;8h21:led_a=8h09;default:led_a=hour;

21、endcaseend/12/24小时切换,24到12,相应BCD码减endendmodule/SEG7_LUT.vmodule SEG7_LUT(iDIG,oSEG);input3:0iDIG;output6:0oSEG;reg6:0oSEG;always (iDIG)begincase(iDIG)4h1: oSEG = 7b;/ -t-4h2: oSEG = 7b; / | |4h3: oSEG = 7b; / lt rt4h4: oSEG = 7b; / | |4h5: oSEG = 7b; / -m-4h6: oSEG = 7b; / | |4h7: oSEG = 7b; / lb rb

22、4h8: oSEG = 7b; / | |4h9: oSEG = 7b; / -b-4ha: oSEG = 7b;4hb: oSEG = 7b;4hc: oSEG = 7b;4hd: oSEG = 7b;4he: oSEG = 7b;4hf: oSEG = 7b;4h0: oSEG = 7b;endcaseendendmodule/divided_frequency.vmodule divided_frequency(_1hzout,ncr,_50mhzin);input _50mhzin, ncr;output _1hzout;supply1 vdd;wire11:0 q;wire _1kh

23、zin;wire en1, en2;divfreq50M_1Khz du00(_1khzin, ncr, _50mhzin);/先调用1khz分频counter10 du0(q3:0, ncr, vdd, _1khzin);counter10 du1(q7:4, ncr, en1, _1khzin);counter10 du2(q11:8, ncr, en2, _1khzin);/再调用三个10计数器,将1khz分为1hzassign en1=(q3:0 = 4h9);assign en2=(q7:4 = 4h9) & (q3:0 = 4h9);assign _1hzout = q11;ass

24、ign _500hzout = q0;endmodule module divfreq50M_1Khz(_1khzout,ncr,_50mhzin);input _50mhzin, ncr;output _1khzout;reg _1khzout;reg15:0 cnt;always (posedge _50mhzin )beginif(ncr)_1khzout=1b0;else beginif(cnt=16d24999)begin _1khzout=_1khzout;cnt=16b0;end/50000分频else cnt=cnt+1b1;endendendmodulemodule divf

25、req50M_5hz(_5hzout,ncr,_50mhzin);input _50mhzin,ncr;output _5hzout;reg _5hzout;reg24:0 cnt;always (posedge _50mhzin )beginif(ncr) _5hzout=1b0;else beginif(cnt=25d) begin _5hzout=_5hzout;cnt=25b0;end/一千万分频else cnt=cnt+1b1;endendendmodule/counter10.vmodule counter10(q,ncr,en,cp);/模十 input cp,ncr,en; o

26、utput 3:0 q; reg 3:0 q; always(posedge cp or negedge ncr) begin if(ncr) q=4b0000; else if (en) q=q; else if(q=4b1001) q=4b0000; else q=q+1b1; endendmodulemodule counter6(q,ncr,en,cp);/模6 input cp,ncr,en; output 3:0 q; reg 3:0 q; always(posedge cp or negedge ncr) begin if(ncr) q=4b0000; else if (en) q=q; else if(q=4b0101) q=4b0000; else q