Verilog-电子琴程序

1、如题,再附加上程序的控制说明.是用GW48教学实验箱仿真的如果对你有帮助,请大家顶上.程序直接贴上了控制说明：1、电子琴：程序设计采用八个输入端口，分别与实验箱上的按键81引脚相连接，采用一个输出端口，与扬声器的引脚连接，时钟频率采用6MHz和4Hz。按键71分别用于中音的七个音符的发音（DO，RE，MI，FA，SO，LA，SI），按键8用于控制乐曲的播放。程序的编写采用状态机的编写方法，对按键的状态进行判断，对应相应的音符或乐曲。2、电子钟：程序的设计模块有：时钟初始化模块、时钟工作模块、时钟设置模块、闹钟设置模块、闰年的月份天数判断模块、数码管显示模块、闹钟铃声模块及其它的设置模块。程序使

2、用8个输入分别与8个按键连接，用按键8对应时钟工作状态（work_state），当work_state为0时，时钟正常工作，当work_state为1时，进入时钟设置状态。按键7对应输入端口display_set控制时钟显示状态（display_state），每按2次（用于产生上升沿触发）则数码管的输出不同。Display_state与work_state相结合使用，以区分设置的参数。按键64对应输入个脚in_set，该参数共有三位，用以表示三个状态：state_yorh （设置年或小时）、state_morm（设置月份或分钟）、 state_dors（设置日期或秒钟）。按键32对应数值设置端

3、口up各down。Up用于产生上升沿触发，当down为0时，则每一个上升沿产生时，相应的参数加1，当down为1时，则每一个上升沿产生时，相应的参数减1。按键1与输入端口clock_on相连，用于闹钟的开与关，当 clock_on为1时开闹钟，否则关闹钟。扬声器与输出端口speaker相连，用于输出闹钟铃声。附录：源程序一、 电子琴：module piano(in,clk_6MHz,clk_4Hz,song,speaker); input in,clk_6MHz,clk_4Hz,song; output speaker; reg speaker; reg7:0 state; reg song_

4、on; wire6:0 in; reg3:0 high,med,low; reg13:0 divider,origin; reg7:0 counter; reg out; wire carry; reg20:0 i; parameter zero=8b0000_0000, one=8b0000_0001, two=8b0000_0010, three=8b0000_0100, four=8b0000_1000, five=8b0001_0000, six=8b0010_0000, seven=8b0100_0000; initial begin song_on=0; end always (p

5、osedge song) begin song_on=song_on; end always (posedge clk_6MHz) begin if(song_on) speaker=out; else begin case(in) zero:begin speaker=0; i=11451) begin speaker=!speaker; i=0; end else i=10204) begin speaker=!speaker; i=0; end else i=9091) begin speaker=!speaker; i=0; end else i=8596) begin speaker

6、=!speaker; i=0; end else i=7653) begin speaker=!speaker; i=0; end else i=6818) begin speaker=!speaker; i=0; end else i=6073) begin speaker=!speaker; i=0; end else i=i+1; end default:begin speaker=0; i=0; end endcase end end assign carry=(divider=16383); always (posedge clk_6MHz) begin if(carry) divi

7、der=origin; else divider=divider+1; end always (posedge carry) begin out=out; /2 分频产生方波信号 end always (posedge clk_4Hz) begin case(high,med,low) /分频比预置 b1: origin=7281; b1: origin=8730; b0: origin=9565; b1: origin=10310; b0: origin=10647; b0: origin=11272; b0: origin=11831; b0: origin=12556; b0: orig

8、in=12974; b0: origin=13516; b0: origin=16383; endcase end always (posedge clk_4Hz) begin if(counter=63) counter=0; /计时，以实现循环演奏 else counter=counter+1; case(counter) /记谱 0: high,med,low=b1; /低音“3” 1: high,med,low=b1; /持续4 个时钟节拍 2: high,med,low=b1; 3: high,med,low=b1; 4: high,med,low=b1; /低音“5” 5: hig

9、h,med,low=b1; /发3 个时钟节拍 6: high,med,low=b1; 7: high,med,low=b0; /低音“6” 8: high,med,low=b0; /中音“1” 9: high,med,low=b0; /发3 个时钟节拍 10: high,med,low=b0; 11: high,med,low=b0; /中音“2” 12: high,med,low=b0; /低音“6” 13: high,med,low=b0; 14: high,med,low=b1; 15: high,med,low=b1; 16: high,med,low=b0; /中音“5” 17:

10、high,med,low=b0; /发3 个时钟节拍 18: high,med,low=b0; 19: high,med,low=b0; /高音“1” 20: high,med,low=b0; 21: high,med,low=b0; 22: high,med,low=b0; 23: high,med,low=b0; 24: high,med,low=b0; /中音“2” 25: high,med,low=b0; /持续11 个时钟节拍 26: high,med,low=b0; 27: high,med,low=b0; 28: high,med,low=b0; 29: high,med,low

11、=b0; 30: high,med,low=b0; 31: high,med,low=b0; 32: high,med,low=b0; 33: high,med,low=b0; 34: high,med,low=b0; 35: high,med,low=b0; /中音“3” 36: high,med,low=b1; /低音“7” 37: high,med,low=b1; 38: high,med,low=b0; /低音“6” 39: high,med,low=b0; 40: high,med,low=b1; /低音“5” 41: high,med,low=b1; 42: high,med,lo

12、w=b1; 43: high,med,low=b0; /低音“6” 44: high,med,low=b0; /中音“1” 45: high,med,low=b0; 46: high,med,low=b0; /中音“2” 47: high,med,low=b0; 48: high,med,low=b1; /低音“3” 49: high,med,low=b1; 50: high,med,low=b0; /中音“1” 51: high,med,low=b0; 52: high,med,low=b0; 53: high,med,low=b1; /低音“5” 54: high,med,low=b0; 55: high,med,low=b0; /中音“1” 56: high,med,lo