计算机组织与结构：版7-11_ Instruction Sets addressing modes

1、1,William Stallings Computer Organization and Architecture7th Edition,Chapter 11 Instruction Sets: Addressing Modes and Formats,2/40,Key terms (1),immediate addressing direct addressing indirect addressing register addressing register indirect addressing displacement (indexed) addressing stack,3/40,

2、Key terms (2),autoindexing base-register addressing effective address relative addressing preindexing postindexing instruction format,4/40,Addressing Modes,Immediate Direct Indirect Register Register Indirect Displacement (Indexed) Stack,5/40,Immediate Addressing,Operand is part of instruction Opera

3、nd = address field e.g. ADD 5 Add 5 to contents of accumulator 5 is operand No memory reference to fetch data Fast Limited range,6/40,Immediate Addressing Diagram,7/40,Direct Addressing,Address field contains address of operand Effective address (EA) = address field (A) e.g. ADD A Add contents of ce

4、ll A to accumulator Look in memory at address A for operand Single memory reference to access data No additional calculations to work out effective address Limited address space,8/40,Direct Addressing Diagram,9/40,Indirect Addressing (1),Memory cell pointed to by address field contains the address o

5、f (pointer to) the operand EA = (A) Look in A, find address (A) and look there for operand e.g. ADD (A) Add contents of cell pointed to by contents of A to accumulator,10/40,Indirect Addressing (2),Large address space 2n where n = word length May be nested, multilevel, cascaded e.g. EA = (A) Draw th

6、e diagram yourself Multiple memory accesses to find operand Hence slower cascade 英音：kskeid 层叠（的） 重叠排列,11/40,Indirect Addressing Diagram,Address A,Opcode,Instruction,Memory,Operand,Pointer to operand,12/40,Register Addressing (1),Operand is held in register named in address filed EA = R Limited numbe

7、r of registers Very small address field needed Shorter instructions Faster instruction fetch,13/40,Register Addressing (2),No memory access Very fast execution Very limited address space Multiple registers helps performance Requires good assembly programming or compiler writing N.B. C programming re

8、gister int a; c.f. Direct addressing N.B.=nota bene(=note well) 【拉】(处方)注意 c.f. 【拉】=compare,14/40,Register Addressing Diagram,15/40,Register Indirect Addressing,C.f. indirect addressing EA = (R) Operand is in memory cell pointed to by contents of register R Large address space (2n) One fewer memory a

9、ccess than indirect addressing,16/40,Register Indirect Addressing Diagram,17/40,Displacement Addressing,EA = A + (R) Address field hold two values A = base value R = register that holds displacement or vice versa Displacement 位移；变位 vice versa 【拉】反之亦然,18/40,Displacement Addressing Diagram,19/40,Relat

10、ive Addressing,A version of displacement addressing R = Program counter, PC EA = A + (PC) i.e. get operand from A cells from current location pointed to by PC c.f locality of reference & cache usage,20/40,Base-Register Addressing,A holds displacement R holds pointer to base address R may be explicit

11、 or implicit e.g. segment registers in 80 x86,21/40,Indexed Addressing,A = base R = displacement EA = A + R Good for accessing arrays EA = A + R R+,22/40,Combinations,Postindex EA = (A) + (R) Preindex EA = (A+(R) (Draw the diagrams),23/40,Stack Addressing,Operand is (implicitly) on top of stack e.g.

12、 ADDPop top two items from stackand add,24/40,Pentium Addressing Modes,Virtual or effective address is offset into segment Starting address plus offset gives linear address This goes through page translation if paging enabled 12 addressing modes available Immediate Register operand Displacement Base

13、 Base with displacement Scaled index with displacement Base with index and displacement Base scaled index with displacement Relative,25/40,Pentium Addressing Mode Calculation,26/40,PowerPC Addressing Modes,Load/store architecture Indirect Instruction includes 16 bit displacement to be added to base

14、register (may be GP register) Can replace base register content with new address Indirect indexed Instruction references base register and index register (both may be GP) EA is sum of contents Branch address Absolute Relative Indirect Arithmetic Operands in registers or part of instruction Floating

15、point is register only,27/40,PowerPC Memory Operand Addressing Modes,28/40,Instruction Formats,Layout of bits in an instruction Includes opcode Includes (implicit or explicit) operand(s) Usually more than one instruction format in an instruction set,29/40,Instruction Length,Affected by and affects:

16、Memory size Memory organization Bus structure CPU complexity CPU speed Trade off between powerful instruction repertoire and saving space Trade off 平衡,30/40,Allocation of Bits,Number of addressing modes Number of operands Register versus memory Number of register sets Address range Address granularity versus 英音：v:ss 与.相对 granularity 间隔尺寸,31/40,PDP-8 Instruction Format,32/40,PDP-10 Instruct