短距离无线通信技术文献翻译

1、 单位代码 01 学 号 分 类 号 TN92 密 级 文献翻译一个新的CMOS通道选择滤波器的双模式蓝牙/ WLAN直接变频接收机 院（系）名称信息工程学院 专业名称电子信息工程 学生姓名xx 指导教师xxxx2013年3月30日一个新的CMOS通道选择滤波器的双模式蓝牙/ WLAN直接变频接收机摘要：设计一个CMOS四阶通道选择滤波器集成双模蓝牙/ WLAN直接变频接收机芯片。 其带宽滤波器可以被编程从200 kHz到8 MHz容纳两个标准。 这种滤波器提供缓慢的权力，和小面积的设计解决方案。布线模拟结果表明，该滤波器满足这两个应用程序的选择性和动态范围的要求，同时消耗1.88 mW的待机

2、功率。关键词：CMOS混合模拟/数字系统，电流型电路，主动滤波器，电流反馈放大1 简介在便携式设备和无线网络的应用程序中，使得无电缆环境发展的愿景更为可行。它是短距离的无线传输系统，如蓝牙（BT）和无线局域网 (WLAN)。这种技术的主要目的是利用低成本、低功耗、体积小的单晶片处理语音和数据。BT 和 WLAN 的体系结构允许使用不同频率的无线接收器：高频、低中频和零频率 (直接转换)。但在双模式操作中，直接转换架构能够最大限度的利用各种构造块电流消耗。因此, 在最小的外部组件中，它提供了一种低功耗、低成本的解决方案。基带混频信号要求混频器的I / Q和单独的基带路径来持负频率的信息。虽然这种

3、体系结构遭受非线性直流偏移引起的自混频问题，但是为了避免饱和校正，可以用直流分量的方法解决直流偏移问题。高动态范围的低通滤波器必须纳入在直接转换器的信道选择。该滤波器的特性占每个接收机性能的主导地位。这是因为，在天线接收到的信号经常包含比所需的频道频率较高的通道。而滤波器必须能够处理大量信号的互调失真。根据系统的规格，输入的射频信号的功率是BT-70dBm和无线局域网-76dBm。然而，满足标准的误码率所需的信噪比在基带BT输出的是21dB,无线局域网输出的是10dB。系统计算表明，这个伪自由动态范围（SFDR）为BT必须超过54dB和WLAN必须超过44.2分贝（dB）。此外,巴特沃斯响应必

4、须被用来满足滤波器所需的群迟延，此时BT应小于1us。另外，发现足以满足4阶滤波器选择性要求的两个标准。此外，BT和WLAN模式的最佳带宽分别是600 KHz和 5.5 MHz。BT/WLAN 双模滤波器可以在各种拓扑的文献中找到。该滤波器使用可编程OTAC。但是，主要的缺点是它使用 BiCMOS 技术，是相对较昂贵的。在有源RC滤波器中采用CMOS技术，但是可编程功能的实现是采用电阻和电容矩阵，从而导致面积相对较大，也限制了调谐分辨率。因此，一个可编程的，大动态范围的滤波器的设计给模拟设计带来一大挑战。传统的CMOS GM -C或MOSFET -C滤波器，或线性化技术参数，在MOS晶体管的应

5、用特征中不能实现高动态范围。同时，当电源电压水平进一步降低时，C滤波器比预期失去更多的动态范围以及调谐范围。另一方面，当前反馈放大器（CFA），具有潜在的高带宽，高转换率，良好的线性度和低功耗的性质。然而，在集成电路应用程序中在缺少可编程性功能。调谐特性必须达到没有失去潜在的优势，特别是它的线性度和CFA频率响应。本文的目的是通过利用电流分工网络（CDN）提供数字调谐CFA的电流增益。CDN是固有的线性（纯正二阶效应），并在所有MOS经营区域，它的操作是有效的。同时，它具有宽的频带（高于200兆赫），它也可以数字调谐10位无组件扩展。此外，它是适用于低功耗操作的，因为它不消耗待机电流。在本文中

6、，基于可编程的 CMOS四阶滤波器CFA通过直接转换接收滤波器实现BT/WLAN的信道选择。布局仿真结果表明滤波器预计将提供动态范围宽，低功耗和可编程性的优势。以下部分描述了数字可编程的电流反馈放大器。第3节中介绍了滤波器组和在第 4 节中提供了仿真结果。2 CMOS可编程CFA这部分简要描述了终端的特点和实现滤波器设计所需的基本构建模块。在集成电路中，连续调谐性能是必不可少的，用滤波技术来补偿工艺，成分和温度的变化是至关重要的。因此,所提出的滤波器包括CFA电流分工网络(CDN)。对于CDN的操作，图1所示，类似于R-2R梯。输入的电流是通过不同的分支的二进制加权。输出电流可以表示为： （1

7、）其中 d 是 th 的数字位，n 为控制字的大小。请注意，CDN的正确的操作需要接入的输入节点是驱动电流而输出节点事实上是接地。CFA是一个四端器件,包括电压缓冲区()之间的一个高输入终端Y和低终端X的电流感应,然后输送到一个高阻抗输出终端Z。此外，第二电压缓冲区（ ）之间采用端子Z和一个低输出阻抗端子W。 CFA理想的终端特性，可以被描述为如下：= (2)在本文中，通过编程的流动比率= ，介绍可编程功能CDN的使用。CDN的正确操作需要电流驱动的输入节点，而其输出节点被假想性地接地。图1 目前的分工网络图 2 提出数字可编程电流反馈放大器拓扑前者的条件可满足采用电流镜（源）输出到一个CDN

8、的输入，如图2所示。而电流跟随器（CF）是用来提供后期的条件，并把高输出阻抗保存在Z端子。CMOS执行的和CF分别如图3和4所示。在这种情况下，CDN处的衰减和输出电流将是： (3)或者，对CDN和CF可以替换为一个数字控制的CF(DCCF) 。其中一个CDN结合内部负反馈的一部分，DCCF基本上是CF。在这种拓扑中，将加剧DCCF和输出电流将是： (4)图3 电压缓冲器（）与电流镜(CM）的CMOS实现图2图4.电流跟随器(CF)CMOS实现图23 推荐的滤波器一个积分器与接地电容可以很轻松的构建CFA。因此，这两个积分回路（Tow Thomas）的拓扑是用于二阶滤波器。所提出的滤波器拓扑结

9、构如图5所示，该电路提供的低通响应由下式给出： (5)因此，转角频率等于3 dB带宽的巴特沃思响应和品质因数将是：图5两个集成回路第二阶段 (6) (7)对于(for i=1,2). 可以看出，在没有改变Q时，和同时可编程且n可调谐。滤波器将允许调整带宽，以适应两种操作模式，同时仍近似保留巴特沃斯。预期的自身阻抗将不会影响滤波器的性能或高达几十兆赫的工作频率。正是由于这样的事实，除了那些在集成电容器，所有内部节点都在低阻抗（即输出端子的VBS）。值得注意的是，CDN- CF实现具有较小的无源元件比基于一个给定的频率调谐范围DCCF拓扑更具有优势。这是因为，CDN- CF拓扑会导致在调谐阶段减少

10、电流增益的值。然而，的DCCF拓扑结构的电流增益调整的频率为。因此，该滤波器在过滤段直接级联，具有高输入阻抗和低输出阻抗。同时，这意味着该滤波器的传递函数是不受源和/或负载阻抗的影响。BT和WLAN被应用于4阶低通滤波器开发级联程序的两个部分。4 仿真结果全微分四阶信道选择滤波器的级联由两个二阶滤波器实现。反馈电路的共模（CM）被纳入CFA，在每个调整的CM的输出电压为零。一个10bit的CDN用于在每个标准和标准之间的切换中精确地选择所需的信道。该10bit的CDN滤波器的带宽可调的准确率达到0.1，其电源电压和总的待机电流分别设置为2.5 V和0.75mA。该过滤器是模拟HSPICE使用B

11、SIM3 0.35m CMOS模型可以通过MOSIS 。布线后的仿真结果显示几个可容纳 BT 和 WLAN 的频率响应，分别如图 6 和图 7所示。在模拟中有源负载电阻为 1 k。对于 BT 的衰减在 2 MHz 阻滞剂是超过 80 分贝，而超过 40 分贝衰减为 25 MHz 阻滞在 WLAN 模式下实现的。图6 所提出的滤波器带宽变化在BT几个反应图7所提出的滤波器带宽变化在WLAN几个反应IIP3的带宽是由BT的27dB和WLAN的22dBm所确定，如图8所示。IIP3的带宽更好的应用于该滤波器测试音调的阻带。滤波器BT和WLAN的输入噪声根谱的密度被认为是几乎恒定在3分贝，通频带与近似

12、值分别为和23nV/,这个值将导致带内SFDR为61 dB的BT和63 dB的WLAN 。因此，过滤器满足的SFDR两个标准。 图8 图形分析，以确定IIP3此外，Monte-Carlo是用来研究分析滤波器在图像中不匹配的抑制比（IRR）。Monte-Carlo分析表现于分别在IRR中查看所有的电容器和电阻器，并用2的标准偏差，进行 100次试验，根据高斯分布，BT和WLAN的平均幅度误差小于0.63.9，而相位误差小于0.91之间，记录结果为-33.5-40 dB。5 总结本文提出了一种集成双模式 BT/WLAN的直接变频接收机的CMOS 通道选择滤波器的设计。布线后的仿真结果表明，本设计满

13、足在面积和功耗方面改进噪声线性度特性选择性的标准要求。该滤波器具有61 d B的BT频段和63 dB的WLAN频段，与它的同行相比，面积减少了33%，且节省了高达72%的能量。来自：Hussain A. Alzaher.中国保监会过程模拟信号（2010）63:5358.附：英文原文A new CMOS channel select lter for dual mode bluetooth/WLAN direct-conversion receiverAbstract：Design of a CMOS 4th-order channel select lter for integrated du

14、al mode Bluetooth/WLAN direct-conversion receiver is presented. The bandwidth of the lter can be programmed from 200 kHz to 8 MHz to accommodate both standards. The proposed lter provides low power, and small area design solution. Post-layout simulation results show that the lter satises the selecti

15、vity and dynamic range requirements of both applications while consuming total standby power of 1.88 mW.Key words: CMOS mixed analog/digital systems, Current-mode circuits., Active lters, Current feedback amplier.1 IntroductionThe recent development in portable devices and wireless network applicati

16、ons has made the vision of cable-free environment more feasible. It is the driving force behind the boom of short-range wireless systems such as Bluetooth (BT) and Wireless Local Area Network (WLAN). The main objective of such technologies is handling voice and data with open standards utilizing low

17、 cost, low power, small size, and single-chip designs. BT and WLAN specications permit the use of different wireless receiver architectures: High-IF, Low-IF, and Zero-IF (Direct Conversion). But the direct-conversion architecture enables the maximum reuse and the optimal current consumption of the v

18、arious building blocks in dual mode operation. Therefore, it provides a low power and low cost solution with the minimal external components. The signal is mixed directly to base-band, requiring I/Q down-mixers and separate base-band paths to maintain the negative frequency information. Although thi

19、s architecture suffers from non-linear DC offset problems caused by self-mixing, DC component can be removed with DC off set correction methods to avoid saturating the receiver .A high dynamic range low pass lter must be incorporated in the direct-conversion receiver for channel selection. The chara

20、cteristics of the lter dominate the performance of the overall receiver. This is because the received signal at the antenna frequently contains adjacent channels with signicantly higher power than the desired channel. The lter must be able to process large signals with little inter-modulation distor

21、tion.According to system specications given in, the input RF signal power is -70dBm for BT, and -76dBm for WLAN. Whereas, the required SNR, to meet the standard BER, at the output of the baseband is 21dB for BT and 10dB for WLAN. System level calculations show that the spurious free dynamic range (S

22、FDR) must be more than 54dB for BT and 44.2dB for WLAN. In addition, Butterworth response must be used to realize the lter in order to satisfy the required in band group delay of BT which should be less than 1s. Moreover, a 4th-order lter is found to be sufficient to meet the selectivity requirement

23、s of both standards. Furthermore, the optimum bandwidth is 600 kHz and 5.5 MHz for the BT and WLAN modes,respectively. Various topologies for BT/WLAN dual-mode lters can be found in the literature. The lters in are built using programmable OTA-C, but the main disadvantage is that it uses BiCMOS tech

24、nology which is relatively expensive. The lter in uses CMOS active RC technique but the programmability feature is achieved using capacitor and resistor matrices, which results in relatively large area and also limits the tuning resolution. Thus, the design of a programmable, large dynamic range lte

25、r represents a major challenge to analog designers. Conventional CMOS -C or MOSFET-C lters, where linearization techniques of MOS transistor characteristics are applied, do not achieve high dynamic range. Also, -C lters are expected to lose more dynamic range as well as tuning range when power-suppl

26、y voltage levels are further reduced. On the other hand, the current feedback amplier (CFA) has potentially high bandwidth, high slew rate, good linearity and low-power consumption. However, the lack of programmability feature hinders its use in integrated circuit applications. Tuning feature must b

27、e achieved without losing the potential advantages of CFA particularly its linearity and frequency response. This objective is accomplished by using the current division network (CDN) to provide digital tuning of the CFAs current gain. The CDN is inherently linear (insensitive to second order effect

28、s) and its operation is valid in all MOS operating regions. Also, it exhibits a wide bandwidth (higher than 200MHz) and it can be digitally tuned up to 10 bits without component spreading. In addition, it is suitable for low power operation since it does not dissipate standby current. In this paper,

29、 a 4th-order lter based on the programmable CMOS CFA is proposed to implement the channel select lter for BT/WLAN direct conversion receiver. Post-layout simulation results show that the lter is expected to provide the advantage of high dynamic range and wide programmability feature with low-power c

30、onsumption. The following section describes the digitally programmable CFA. The proposed lter is presented in Sect.3 and simulation results are provided in Sect.4. 2 A CMOS programmable CFAThis section briey describes the terminal characteristics and realizations of the basic building blocks needed

31、in the lter design. Tuning properties are essential for continuous time integrated circuit ltering techniques to compensate for process, component and temperature variations. Thus, the proposed CFA based lter comprises the current division network (CDN). The operation of the CDN, shown in Fig.1, is

32、similar to that of the R-2R ladder.The input current is binary weighted through the different branches. The output current can be expressed as: （1）Where is the th digital bit and n is the size of control word. Note that the proper operation of the CDN requires the input node to be current driven whi

33、le the output node to be virtually grounded. CFA is a four terminal device which consists of a voltage buffer ()between a high input terminal Y and a low terminal X whose current is sensed and conveyed to a high output impedance terminal Z. Also, a second voltage buffer () is employed between termin

34、al Z and a low output impedance terminal W. The ideal terminal characteristics of a CFA can be described as follows: = (2)In this paper, the CDN is utilized to introduce programmability feature through programming the current ratio =. The proper operation of the CDN requires its input node to be cur

35、rent driven while its output node to be virtually grounded. Fig.1 The current division networkFig.2 Proposed digitally programmable CFA topologyThe former condition can be satised by applying the current mirror output to the input of a CDN as shown in Fig.2. Whereas a current follower (CF) is used t

36、o provide the later condition and preserve a high output impedance at the Z terminal. The CMOS implementation of and the CF are shown in Figs.3 and 4, respectively. In this case, will be attenuated by the CDN and the output current will be: （3）Alternatively, the CDN and the CF can be replaced by a d

37、igitally controlled CF (DCCF). The DCCF is basically a CF wherein a CDN is incorporated as a part of internal negative feedback. In this topology, will be amplied by the DCCF and the output current will be: (4)Fig.3 Voltage buffer () CMOS implementation with current mirrors (CM) for Fig. 2Fig. 4 Cur

38、rent follower (CF) CMOS implementation for Fig. 23 Proposed lterAn integrator with grounded capacitor can be easily built using CFA. Therefore, the two integrator loop (Tow Thomas) topology is used for the biquadratic lter. The proposed lter topology is shown in Fig.5. It can be shown that the circu

39、it provides lowpass response given by: (5)Therefore, the corner frequency, which is equal to the -3dB bandwidth for the Butterworth response, and the quality factor will be: Fig.5 Two integrator-loop second-order section (6) (7)where(for =1,2). It can be seen that can be tuned digitally without chan

40、ging Q by programming and simultaneously. This will allow adjusting the bandwidth of the lter to accommodate the two operating modes while still preserving Butterworth approximation. It is expected that the parasitic impedances will not affect the lter performance or operating frequencies up to a fe

41、w tens of MHz. This is due to the fact that all internal nodes, except those of the integrating capacitors, are at low impedance (i.e. output terminals of theVBs). Note that the CDN-CF realization has the advantage of requiring smaller passive elements than their counterparts based on the DCCF topol

42、ogy for a given frequency tuning range. This is because that the CDN-CF topology exhibits current gain of which will result in reducing the value of during the tuning phase. Whereas, for the DCCF topology the current gain will be which would tune up in frequency. The proposed lter has a high input i

43、mpedance and low output impedance, therefore the lter sections are directly cascadable. Also, this means that the lter transfer function is not affected by the source and/or the load impedances. A 4th-order lowpass lter for dual BT and WLAN application can be developed by cascading two sections. 4 S

44、imulation resultsA fully differential 4th-order channel select lter is realized by cascading two biquads. A common-mode (CM) feedback circuit is incorporated to adjust the CM output voltage to zero in each CFA. A 10-bit CDN is used for both precisely selecting the desired channel within each standar

45、d and switching between the standards. With 10-bit CDN the lter bandwidth can be tuned up to 0.1% accuracy. The supply voltage and the total standby current of the lter were set to 2.5V and about 0.75mA, respectively. The lter was simulated with HSPICE using BSIM3 0.35 m CMOS models available throug

46、h MOSIS. Post-layout simulation results showing several frequency responses accommodating BT and WLAN are given in Figs.6 and 7, respectively. A source and a load resistance of 1k each are used in simulations. For BT the attenuation at the 2MHz blocker is more than 80dB. Whereas, more than 40dB attenuation is achieved for the 25MHz blocker in the WLAN mode. Fig.6 Several responses of the proposed lter varied around the bandwidth for BTFig.7 Several responses of the proposed lter varied around the bandwidth for WLANThe in