电气工程及其自动化毕业设计（论文）外文翻译-基于AT89C51的程控数字电压表.doc

南 京 理 工 大 学 紫 金 学 院毕业设计(论文)外文资料翻译系： 电子工程及光电技术系 专 业： 电气工程及其自动化 姓 名： 付仁龙 学 号： 080405109 (用外文写)外文出处： /view/c472824ae45 c3b3567ec8b18.html 附 件： 1.外文资料翻译译文；2.外文原文。 指导教师评语： 该生所选外文难度适中，译文基本符合原文的内容和思想。语句通顺，流利，专业用语较恰当。意思表达合理，完整。成 绩签 名年 月 日注：请将该封面与附件装订成册。附件1：外文资料翻译译文 at89c51的概况1 at89c51应用单片机广泛应用于商业：诸如调制解调器，电动机控制系统，空调控制系统，汽车发动机和其他一些领域。这些单片机的高速处理速度和增强型外围设备集合使得它们适合于这种高速事件应用场合。然而，这些关键应用领域也要求这些单片机高度可靠。健壮的测试环境和用于验证这些无论在元部件层次还是系统级别的单片机的合适的工具环境保证了高可靠性和低市场风险。intel 平台工程部门开发了一种面向对象的用于验证它的at89c51 汽车单片机多线性测试环境。这种环境的目标不仅是为at89c51 汽车单片机提供一种健壮测试环境，而且开发一种能够容易扩展并重复用来验证其他几种将来的单片机。开发的这种环境连接了at89c51。本文讨论了这种测试环境的设计和原理，它的和各种硬件、软件环境部件的交互性，以及如何使用at89c51。1.1 介绍8 位at89c51 chmos 工艺单片机被设计用于处理高速计算和快速输入/输出。mcs51 单片机典型的应用是高速事件控制系统。商业应用包括调制解调器，电动机控制系统，打印机，影印机，空调控制系统，磁盘驱动器和医疗设备。汽车工业把mcs51 单片机用于发动机控制系统，悬挂系统和反锁制动系统。at89c51 尤其很好适用于得益于它的处理速度和增强型片上外围功能集，诸如：汽车动力控制，车辆动态悬挂，反锁制动和稳定性控制应用。由于这些决定性应用，市场需要一种可靠的具有低干扰潜伏响应的费用-效能控制器，服务大量时间和事件驱动的在实时应用需要的集成外围的能力，具有在单一程序包中高出平均处理功率的中央处理器。拥有操作不可预测的设备的经济和法律风险是很高的。一旦进入市场，尤其任务决定性应用诸如自动驾驶仪或反锁制动系统，错误将是财力上所禁止的。重新设计的费用可以高达500k 美元，如果产品族享有同样内核或外围设计缺陷的话，费用会更高。另外，部件的替代品领域是极其昂贵的，因为设备要用来把模块典型地焊接成一个总体的价值比各个部件高几倍。为了缓和这些问题，在最坏的环境和电压条件下对这些单片机进行无论在部件级别还是系统级别上的综合测试是必需的。intel chandler 平台工程组提供了各种单片机和处理器的系统验证。这种系统的验证处理可以被分解为三个主要部分。系统的类型和应用需求决定了能够在设备上执行的测试类型。1.2 at89c51提供以下标准功能：4k 字节flash 闪速存储器，128 字节内部ram，32 个i/o 口线，2 个16 位定时/计数器，一个5 向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，at89c51 降至0hz 的静态逻辑操作，并支持两种可选的节电工作模式。空闲方式体制cpu 的工作，但允许ram，定时/计数器，串行通信口及中断系统继续工作。掉电方式保存ram 中的内容，但振荡器体制工作并禁止其他所有不见工作直到下一个硬件复位。 图1-2-1 at89c51 方框图1.3引脚功能说明vcc：电源电压gnd：地p0 口：p0 口是一组8 位漏极开路型双向i/o 口，也即地址/数据总线复用。作为输出口用时，每位能吸收电流的方式驱动8 个ttl 逻辑门电路，对端口写“1”可作为高阻抗输入端用。在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8 位）和数据总线复用，在访问期间激活内部上拉电阻。在flash 编程时，p0 口接受指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。p1 口：p1 是一个带内部上拉电阻的8 位双向i/o 口，p1 的输出缓冲级可驱动（吸收或输出电流）4 个ttl 逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作为输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（iil）。flash 编程和程序校验期间，p1 接受低8 位地址。p2 口：p2 是一个带有内部上拉电阻的8 位双向i/o 口，p2 的输出缓冲级可驱动（吸收或输出电流）4 个ttl 逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作为输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（iil）。在访问外部程序存储器或16 位四肢的外部数据存储器（例如执行movx dptr指令）时，p2 口送出高8 位地址数据，在访问8 位地址的外部数据存储器（例如执行movx ri 指令）时，p2 口线上的内容（也即特殊功能寄存器（sfr）区中r2 寄存器的内容），在整个访问期间不改变。flash 编程和程序校验时，p2 也接收高位地址和其他控制信号。p3 口：p3 是一个带有内部上拉电阻的8 位双向i/o 口，p3 的输出缓冲级可驱动（吸收或输出电流）4 个ttl 逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作为输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（iil）。p3 口还接收一些用于flash 闪速存储器编程和程序校验的控制信号。rst：复位输入。当振荡器工作时，rst 引脚出现两个机器周期以上高电平将使单片机复位。ale/prog：当访问外部程序存储器或数据存储器时，ale（地址锁存允许）输出脉冲用于锁存地址的低8 位字节。即使不访问外部存储器，ale 仍以时钟振荡频率的1/6 输出固定的正脉冲信号，因此它可对外输出时钟或用于定时目的。要注意的是，每当访问外部数据存储器时将跳过一个ale 脉冲。对flash 存储器编程期间，该引脚还用于输入编程脉冲（prog）。如有必要，可通过对特殊功能寄存器（sfr）区中的8eh 单元d0 位置位，可禁止ale 操作。该位置位后，只有一条movx 和movc 指令ale 才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ale 无效。psen：程序存储允许输出是外部程序存储器的读选通型号，当89c51 由外部存储器取指令（或数据）时，每个机器周期两次psen 有效，即输出两个脉冲。在此期间，当访问外部数据存储器，这两次有效的psen 信号不出现。ea/vpp：外部访问允许。欲使cpu 仅访问外部程序存储器（地址为0000hffffh），ea 端必须保持低电平（接地）。需注意的是：如果加密位lb1 被编程，复位时内部会锁存ea 端状态。如ea 端为高电平（接vcc 端），cpu 则执行内部程序存储器中的指令。flash 存储器编程时，该引脚加上+12v 的编程允许电源vpp，当然这必须是该器件使用12v 编程电压vpp。xtal1：振荡器反相放大器及内部时钟发生器的输入端。xtal2：振荡器反相放大器的输出端。89c51 中有一个用于构成内部振荡器的高增益反相放大器，引脚xtal1 和xtal2分别是该放大器的输入端和输出端。这个放大器与作为反馈元件的片外石英晶体或陶瓷谐振器一起构成自激振荡器，振荡电路参见图5。外接石英晶体或陶瓷谐振器及电容c1、c2 接在放大器的反馈回路中构成并联振荡电路。对电容c1、c2 虽没有十分严格的要求，但电容容量的大小会轻微影响振荡频率的高低、振荡器工作的稳定性、起振的难易程度及温度稳定性，如果使用石英晶体，我们推荐电容使用30pf10 pf，而如使用陶瓷谐振器建议选择40pf10pf。用户也可以采用外部时钟。这种情况下，外部时钟脉冲接到xtal1 端，即内部时钟发生器的输入端xtal2 则悬空。掉电模式：在掉电模式下，振荡器停止工作，进入掉电模式的指令是最后一条被执行的指令，片内ram 和特殊功能寄存器的内容在终止掉电模式前被冻结。推出掉电模式的唯一方法是硬件复位，复位后将重新定义全部特殊功能寄存器但不改变ram 中的内容，在vcc 恢复到正常工作电平前，复位应无效，且必须保持一定时间以使振荡器重启动并稳定工作。89c51 的程序存储器阵列是采用字节写入方式编程的，每次写入一个字符，要对整个芯片的eprom 程序存储器写入一个非空字节，必须使用片擦除的方法将整个存储器的内容清楚。2 编程方法编程前，设置好地址、数据及控制信号，编程单元的地址加在p1 口和p2 口的p2.0p2.3（11 位地址范围为0000h0fffh），数据从p0口输入，引脚p2.6、p2.7 和p3.6、p3.7 的电平设置见表6，pseb 为低电平，rst保持高电平，ea/vpp 引脚是编程电源的输入端，按要求加上编程电压，ale/prog引脚输入编程脉冲（负脉冲）。编程时，可采用420mhz 的时钟振荡器，89c51 编程方法如下：在地址线上加上要编程单元的地址信号在数据线上加上要写入的数据字节。激活相应的控制信号。在高电压编程方式时，将ea/vpp 端加上+12v 编程电压。每对flash 存储阵列写入一个字节或每写入一个程序加密位，加上一个ale/prog 编程脉冲。改变编程单元的地址和写入的数据，重复15 步骤，知道全部文件编程结束。每个字节写入周期是自身定时的，通常约为1.5ms。数据查询89c51 单片机用数据查询方式来检测一个写周期是否结束，在一个写周期中，如需要读取最后写入的那个字节，则读出的数据的最高位（p0.7）是原来写入字节的最高位的反码。写周期开始后，可在任意时刻进行数据查询。2.1ready/busy:字节编程的进度可通过ready/busy 输出信号检测，编程期间，ale 变为高电平“h”后p3.4（ready/busy）端被拉低，表示正在编程状态（忙状态）。编程完成后，p3.4 变为高电平表示准备就绪状态。程序校验：如果加密位lb、lb2 没有进行编程，则代码数据可通过地址和数据线读回原编写的数据，采用下图的电路，程序存储器的地址由p1 口和p2 口的p2.0p2.3 输入，数据由p0 口读出，p206、p2.7 和p3.6、p3.7 的控制信号见表6，psen 保持低电平，ale、ea 和rst 保持高电平。校验时，p0 口必须接上10k 左右的上拉电阻。图2-1-1 编程电路 图2-2-2 校验电路2.2芯片擦除:利用控制信号的正确组合(表6)并保持ale/prog 引脚10ms 的低电平脉冲宽度即可将eprom 阵列(4k 字节)和三个加密位整片擦除,代码阵列在片擦除操作中将任何非空单元写入”1”,这步骤需在编程之前进行。2.3读片内签名字节:89c51 单片机内有3 个签名字节,地址为030h、031h 和032h。于声明该器件的厂商、号和编程电压。读签名字节的过程和单元030h、031h 和032h的正常校验相仿，只需要将p3.6 和p3.7 保持低电平，返回值意义如下：(030h) = 1eh 声明产品由atmel 公司制造。(031h) = 51h 声明为89c51 单片机。(032h) = ffh 声明为12v 编程电压。(032h) = 05h 声明为5 编程电压。2.4 编程接口：采用控制信号的正确组合可对flash 闪速存储阵列中的每一代码字节进行写入和存储器的整片擦除，写操作周期是自身定时的，初始化后它将自动定时到操作完成。微机接口实现两种信息形式的交换。在计算机之外，由电子系统所处理的信息以一种物理信号形式存在，但在程序中，它是用数字表示的。任一接口的功能都可分为以某种形式进行数据库变换的一些操作，所以外部和内部形式的转换是由许多步骤完成的。模拟-数字转换器（adc）用来将连续变化信号变成相应的数字量，这数字量可是可能性的二进制数值中的一固定值。如果传感器输出不是连续变化的，就不需模拟-数字转换。这种情况下，信号调理单元必须将输入信号变换成为另一信号，也可直接与接口的下一部分，即微计算机本身的输入输出单元相连接。输出接口采用相似的形式，明显的差别在于信息流的方向相反；是从程序到外部世界。这种情况下，程序可称为输出程序，它监督接口的操作并完成数字-模拟转换器（dac）所需数字的标定。该子程序依次送出信息给输出器件，产生相应的电信号，由dac 转换成模拟形式。最后，信号经调理（通常是放大）以形成适应于执行器操作的形式。在微机电路中使用的信号几乎总是太小而不能被直接地连到“外部世界”，因而必须用某种形式将其转换成更适宜的形式。接口电路部分的设计是使用微机的工程师所面临最重要的任务之一。我们已经了解到微机中，信号以离散的位形式表示。当微机要与只有打开或关闭操作的设备相连时，这种数字形式是最有用的，这里每一位都可表示一开关或执行器的状态。为了解决实际问题，一个单片机不仅包括cpu，程序和数据存储器，另外，它必须含有通过cpu 访问外部信息的硬件。一旦cpu 收集到数据信息和流程，它必须能够改变外部领域的一部分，这些硬件设备称作外围设备，它们是cpu 通往外部的窗口。单片机可利用外围设备中最基本的用于一般用途的i/o 接口，每个i/o 接口既可作为输入端又可作为输出端，每个i/o 接口的功能取决与程序初始化阶段对数据方位寄存器相应位进行置一和清零操作，通过cpu 指令对数据寄存器相应位进行置一和清零来置一和清零输出端口，同样输入端口逻辑位也可以通过cpu 指令访问。一些类型的串行口单元允许cpu 与外部设备进行串口通信，用串口位代替平行位进行通信需要少许的i/o 口，这样使通信费用降低但速度也相对慢些。串口传送可以同步也可以异步。附件2：外文原文the general situation of at89c51chapter 1 the application of at89c51microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. the high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. however, these critical application domains also require that these microcontrollers are highly reliable. the high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. intel plaform engineering department developed an object-oriented multi-threaded test environment for the validation of its at89c51 automotive microcontrollers. the goals of thisenvironment was not only to provide a robust testing environment for the at89c51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. the environment was developed in conjunction with microsoft foundation classes (at89c51). the paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use at89c51.1.1 introductionthe 8-bit at89c51 chmos microcontrollers are designed to handle high-speedcalculations and fast input/output operations. mcs 51 microcontrollers are typically used for high-speed event control systems. commercial applications include modems,motor-control systems, printers, photocopiers, air conditioner control systems, disk drives,and medical instruments. the automotive industry use mcs 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (abs). the at89c51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a cpu with above average processing power in a single package. the financial and legal risk of having devices that operate unpredictably is very high. once in the market, particularly in mission criticalapplications such as an autopilot or anti-lock braking system, mistakes are financiallyprohibitive. redesign costs can run as high as a $500k, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. in addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. to mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions.this complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.intel chandler platform engineering group provides post silicon system validation (sv) of various micro-controllers and processors. the system validation process can be broken into three major parts.the type of the device and its application requirements determine which types of testing are performed on the device.1.2 the at89c51 provides the following standard features: 4kbytes of flash, 128 bytes of ram, 32 i/o lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duple ser -ial port, on-chip oscillator and clock circuitry.in addition, the at89c51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. the idle mode stops the cpu while allowing the ram, timer/counters,serial port and interrupt sys -tem to continue functioning. the power-down mode saves the ram contents but freezes the oscil lator disabling all other chip functions until the next hardware reset.figure 1-2-1block diagram1-3pin descriptionvcc supply voltage.gnd ground.port 0：port 0 is an 8-bit open-drain bi-directional i/o port. as an output port, each pin cansink eight ttl inputs. when 1s are written to port 0 pins, the pins can be used as highimpedance inputs.port 0 may also be configured to be the multiplexed loworder address/data busduring accesses to external program and data memory. in this mode p0 has internalpullups.port 0 also receives the code bytes during flash programming,and outputs the codebytes during program verification. external pullups are required during programverification.port 1：port 1 is an 8-bit bi-directional i/o port with internal pullups.the port 1 output buffers can sink/so -urce four ttl inputs.when 1s are written to port 1 pins they are pulled high by the internal pullups and can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current (iil) because of the internal pullups.port 1 also receives the low-order address bytes during flash programming and verification.port 2：port 2 is an 8-bit bi-directional i/o port with internal pullups.the port 2 outputbuffers can sink/source four ttl inputs.when 1s are written to port 2 pins they arepulled high by the internal pullups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current (iil) because of the internal pullups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to port 2 pins that are externally being pulled low will source current (iil) because of the internal pullups.port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movxdptr). in this application, it uses strong internal pull-ups when emitting 1s. during accesses to external data memory that use 8-bit addresses (movx ri), port 2 emits the contents of the p2 special function register.port 2 also receives the high-order address bits and some control signals durin flash programming and verification.port 3：port 3 is an 8-bit bi-directional i/o port with internal pullups.the port 3 outputbuffers can sink/sou -rce four ttl inputs.when 1s are written to port 3 pins they are pulled high by the internal pullups and can be used as inputs. as inputs,port 3 pins that are externally being pulled low will source current (iil) because of the pullups.port 3 also serves the functions of various special featuresof the at89c51 as listed below:rst：reset input. a high on this pin for two machine cycles while the oscillator is running resets the device.ale/prog：address latch enable output pulse for latching the low byte of the address duringaccesses to external memory.this pin is also the program pulse input (prog) during flash programming.in normal operation ale is emitted at a constant rate of 1/6 the oscillator frequency,and may be used for external timing or clocking purposes. note, however, that one alepulse is skipped duri -ng each access to external datamemory.if desired, ale operationcan be disabled by setting bit 0 of sfr location 8eh. with the bit set, ale is active onlyduring a movx or movc instruction. otherwise, the pin is weakly pulled high. settingthe ale-disable bit has no effect if the microcontroller is in external execution mode.psen：program store enable is the read strobe to external program memory. when theat89c51 is executing code from external program memory, psen is activated twiceeach machine cycle, except that two psen activations are skipped during each access toexternal data memory.ea/vpp：external access enable. ea must be strapped to gnd in order to enable the deviceto fetch code from external program memory locations starting at 0000h up to ffffh.note, however, that if lock bit 1 is programmed, ea will be internally latched onreset.ea should be strapped to vcc for internal program executions. this pin alsreceives the 12-volt programming enable voltage (vpp) during flash programming, forparts that require 12-volt vpp.xtal1：input to the inverting oscillator amplifier and input to the internal clock operatingcircuit. xtal2 ：output from the inverting oscillator amplifier.oscillator characteristicsxtal1 and xtal2 are the input and output, respectively, of an inverting amplifierwhich can be configured for use as an on-chip oscillator, as shown in figure 1. either aquartz crystal or ceramic resonator may be used. to drive the device from an externalclock source, xtal2 should be left unconnected while xtal1 is driven as shown in figure 2.there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. idle mode in idle mode, the cpu puts itself to sleep while all the onchip peripherals remain active. the mode is invoked by software. the content of the on-chip ram and all the special functions registers remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hardware reset. it should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write to a port pin when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. power-down modein the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. the on-chip ram and special function registers retain their values until the power-down mode is terminated. the only exit from power-down is a hardware reset. reset redefines the sfrs but does not change the on-chip ram. the reset should not be activated before vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.the at89c51 code memory array is programmed byte-bybyte in either programming mode. to program any nonblank byte in the on-chip flash memory, the entire memory must be erased using the chip erase mode.2 programming algorithmbefore programming the at89c51, the address, data and control signals should be set up according to the flash programming mode table and figure 3 and figure 4. to program the at89c51, take the following steps.1. input the desired memory location on the address lines.2. input the appropriate data byte on the data lines. 3. activate the correct combination of control signals. 4. raise ea/vpp to 12v for the high-voltage programming mode. 5. pulse ale/prog once to program a byte in the flash array or the lock bits. the byte-write cycle is self-timed and typically takes no more than 1.5 ms. repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. data polling: the at89c51 features data polling to indicate the