BSDL-概述

BSDL (Boundary Scan Description Language) 概述,目 錄什麼是 BSDL (What is BSDL)? BSDL 實體敘述 (BSDL Entity Description).BSDL 參數敘述 (BSDL Parameter Description).BSDL 邏輯埠敘述 (BSDL Logical Port Description).BSDL Use 文句 (BSDL Use Statement).腳端分配 (Pin Mapping (s).掃瞄器識別(Scanner Identification)指令暫存器敘述 (Instruction Register Description).暫存器輸入輸出敘述 (Register Access Description).邊界掃描暫存器敘述 (Boundary Register Description).BSDL Hardware Test Validation Detail.,1. 什麼是 BSDL (What is BSDL)(1)?,BSDL 的目的 : Multiple vendors 提供一種 Common language, 在不同的測試設備裡實施 boundary scan 測試, BSDL 已經成為超高速 IC 硬體敘述語言 (VHDL: Very High Speed IC Hardware Description Language) 之子集合 (subset), 並敘述如何將 JTAG 測試裝配於 component 及如何使其動作之語 言, BSDL 可以用於 1149.X 標準測試工具及提供可讀取之資料格式 (data format). 支持 1149.1 標準的 Multiple vendors 會提供 User 相關的 BSDL descriptions, 包括讀取 serial JTAG chain 和促進測試設備的產量, BSDL descriptions 文件內容如下: 1. Describe the test logic. 2. Synthesize the test logic. 3. Enable the generation of a test for a loaded board.4. Length and structure of the boundary scan register. 5. Binary instruction codes. 6. Device identification code. 7. Availability of the TRST pin.8. Physical locations of the JTAG pins.PS : 第 3 項最重要, 當使用 JTAG 進行測試時, 在 BSDL 文件裡, User 能夠決定需要的 bit sequences.,1. 什麼是 BSDL (What is BSDL)(2)?,記述某元件JTAG測試安裝的BSDL敘述,由以下要素構成: BSDL 實體敘述 (BSDL Entity Description). BSDL 參數敘述 (BSDL Parameter Description). BSDL 邏輯埠敘述 (BSDL Logical Port Description). BSDL Use 文句 (BSDL Use Statement). 腳端分配 (Pin Mapping (s). 掃瞄器識別(Scanner Identification) 指令暫存器敘述 (Instruction Register Description). 暫存器輸入輸出敘述 (Register Access Description). 邊界掃描暫存器敘述 (Boundary Register Description).以下對以上9要素逐一加以說明,並舉雙核心Intel Xeon 處理器 2.80 GHz的BSDL敘述為例,2. BSDL 實體敘述 (BSDL Entity Description),所謂實體敘述,可在實體上附加名稱.以entity語句開始,以end語句終止. 例: entity PXV_0 is 敘述實體內容文字進駐此大括弧內 end PXV_0;- Entity: marks the beginning of a block of statements that outline the overall description of a device.-實體內容文字: 包括以下幾個部份: Generic Parameter Logical Port Description Use Statement Package Pin Mapping Scan Port Identification TAP Description Boundary Register Description -End: marks the end of an entity, package, or package body.,3. BSDL 參數敘述 (BSDL Parameter Description),所謂參數敘述,是來自實體外界的引數(argument),或者如同封裝體形式等事先已決定的參數.例: Generic (PHYSICAL_PIN_MAP: string:=PXV_PGAN); -Generic: selects among several packaging options for a device.,4. BSDL 邏輯埠敘述 (BSDL Logical Port Description),所謂邏輯埠敘述,除了將邏輯名稱給與I/O腳端,同時也將輸入專用、輸出專用,或双方向用等I/O脚端的性质，加以显示出来。例: Port （OE: in bit; Y: out bit_vector(1 to 3); A: in bit_vector(1 to 3); GND, VCC, NC: linkage bit; TDO: out bit; TMS, TDI, TCK: in bit);-Port: assigns meaningful symbolic names to the devices systemterminal.,5. BSDL Use 文句 (BSDL Use Statement),所謂use語句，可參閱在封裝體與封裝體本體所發現的外界定義.例如: use STD_1149_1_1994.all; use PAXVILLE_PACKAGE.all;-use: identifies a VHDL package needed to define the attributesfor a device.,6. 腳端分配 (Pin Mapping (s),所謂腳端分配,是將邏輯信號分配給特定元件的物理性腳端.例如: attribute PIN_MAP of PXV_0 : entity is PHYSICAL_PIN_MAP; constant PXV_PGAN : PIN_MAP_STRING := A: (C8, C9, A7, A6, B7, C11, D12,E13, B8, A9, -attribute-PIN_MAP: declares the pin mapping function for a device.-attribute-REGISTER_ACCESS: tells software that registers other than those prescribed by the IEEE Standard are present.,7. 掃描埠識別 (Scanner Identification),所謂掃瞄埠識別語句,是將文件的TAP加以下定義.例如: attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_RESET of TRST : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (16.0e6, both);-attribute-TAP_SCAN_IN: identifies the devices Test Data In (TDI) port. -attribute-TAP_SCAN_MODE: identifies the devices Test Mode Select (TMS) port. -attribute-TAP_SCAN_OUT: identifies the devices Test Data Out (TDO) port.-attribute-TAP_SCAN_RESET: identifies the devices Test Reset (TRST) port.-attribute-TAP_SCAN_CLOCK: describes the devices Test Clock (TCK) port.,7. 指令暫存器敘述 (Instruction Register Description),所謂指令暫存器敘述,是可識別指令暫存器的元件依存特徵.例如: attribute Instruction_Length of PXV_0: entity is 7; attribute Instruction_Opcode of PXV_0: entity is EXTEST ( 0000000 ), -attribute-INSTRUCTION_LENGTH: defines the length of the devices Instruction Register. -attribute-INSTRUCTION_OPCODE: identifies the operation codes of the Instruction Register.-attribute-INSTRUCTION_CAPTURE: states what bit pattern is loaded into the InstructionRegister at CAPTURE_IR.-attribute-INSTRUCTION_PRIVATE: identifies opcodes that are private and potentially unsafe.-attribute-INSTRUCTION_DISABLE: identifies an opcode that makes a device three-state forin-circuit tests.,8. 暫存器輸入輸出敘述 (Register Access Description),所謂暫存器輸入輸出敘述,是針對各個指令,對該暫存器如何位在TDI與TDO間加以下定義. attribute Register_Access of PXV_0: entity is BOUNDARY (EXTEST, SAMPLE), -attribute-REGISTER_ACCESS: tells software that registers other than those prescribed by the IEEE Standard are present.,9. 邊界掃描暫存器敘述 (Boundary Register Description),所謂邊界掃描暫存器數敘述,是定義有關邊界掃描BSC (Boundary scan cell),所含BSC形式及相關控制的資訊. attribute BOUNDARY_LENGTH of PXV_0: entity is 178; attribute BOUNDARY_REGISTER of PXV_0 : entity is- 0 (BS_4, LINT1, input, X ), -attribute-BOUNDARY_LENGTH: defines the number of cells in the Boundary Register.-attribute-BOUNDARY_REGISTER: describes the Boundary Register itself.-attribute-BOUNDARY_CELLS: identifies which cells are used in the Boundary Register.,10. BSDL Hardware Test Validation Detail (1),本章節提供 JTAG BSDL 512 Verifier 及 Asset ScanWorks 驗證 BSDL 的功能說明.,BSDL Generation and Verification Process,JTAG BSDL Generation/Verification System(BSDL 512 Verifier),BDSL Verifier and Generation software : Automatic adapter wiring generation software.BSDL 512 verifier hardware : supporting up to 512 I/O channels. J