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5.2 Boolean Algebra and Logic Circuit布尔代数与逻辑电路Boolean Algebra 布尔代数Logic Circuit 逻辑电路Logic Gate 逻辑门mathematical logic数理逻辑logic variable 逻辑变量logic operation 逻辑运算expression 表达式AND operation 与运算 AND gate 与门function table 真值表，函数表，功能表 OR operation 或运算 OR gate或门NOT operation 非运算 complement 补码，反码Inversion 取反 ，反向 Inverter 反相器De Morgans Theorem 摩根定理identity 恒等式composite operations 复合运算NAND 与非 NOR 或非integrated circuit 集成电路logic flow diagram 逻辑流程图Flip-Flop（FF） 触发器memory characteristic 记忆特性SET 置位 CLEAR 复位symmetrical 对称的illegal 非法的internal内部的 circuitry 电路, 线路memory element 存储元件, 记忆元件burglar alarm 防盗报警器deactivate 使无效，使不活动photocell 光电池 ，光电管illuminate 照明，照亮saturated 饱和的 activate 使动作，使活动synchronous 同步的 sequential 顺序的synchronous sequential system 同步时序系统synchronize v.同步 master clock 主时钟periodic 周期的 pulse 脉冲periodic pulse 周期脉冲square wave 方波 duty cycle 占空比interval 时间间隔，间隔rising edge 上升沿 falling edge 下降沿positive-going edge 正向沿negative-going edge 负向沿clocked flip-flop 时钟触发器frequency 频率 propagation delays 传播延迟trigger 触发waveforms 波形 trigger input 触发脉冲输入control input 控制输入edge-triggered 边沿触发 triangle 三角形Boolean Algebra and Logic Gates The section is concerned with digital system variables that take on only two values (binary variables). We conventionally denote these values as “0”and”1”,and then use a special set of rules called Boolean algebra to summarize the various ways in which digital variables can be combined. This algebra and much of the notation are adopted directly from mathematical logic. Thus, ”logic variable ”or “logic operation” are commonly used in place of “digital variable” or “digital operation”. Definition of the AND operation: Given two input variables, A and B, and an output variable C, the expression. C=A and B means C=1 if A=1 and B=1otherwise C=0 A circuit that performs the AND operation is called an AND gate. The logic symbol for a two-input AND gate is shown in Figure 5.3.A dot is used as a shorthand for the AND operation, so that Eq.5.2 may be written C=A B, the dot is often omitted simplifying further C=AB.布尔代数和逻辑门本节是有关数字系统的变量就只有两个值（二进制变量）。我们传统上表示为“0”和“1”这些值，然后使用一组特殊的规则称为布尔代数，总结在其中数字变量可以组合各种方法。这个代数和符号多采用直接从数理逻辑。因此，“逻辑变量”或“逻辑运算”是常在“数字变量”或“数字经营”代替。的定义及操作：给定两个输入变量，A和B和一个输出变量C的表达。 = A和B指 = 1如果A = 1和B = 1否则C = 0的一个电路，执行和操作被称为与门。对于一个二输入与门，如图5.3所示的逻辑符号。一个点是作为与操作使用速记，使Eq.5.2可以写作C = AB，点往往省略进一步简化 = AB。One nice feature of digital operations is that the complete set of input output variable values can be written down. Figure 5.3(a)shows such a function table, corresponding to equation C=AB, which lists all possible combinations of input variables A and B together with the corresponding output variable C. From this function table we see that in algebraic terms the AND operation is a form of multiplication, with these manipulation rules: Definition of the OR operation: Given two input D and E, and an output variable F, the expression F=D OR EMeans F=1 if D=1 or E=1 or both D=1 and E=1The +sign is used as a shorthand for OR, and is never omitted in algebraic expressions, Thus, Eq.5.5 is written algebraically as F=D+EFigure 5.3(b) shows the logic symbol used for the two-input OR gate together with the corresponding function table. Algebraically, the OR operation is a special form of addition performed according to these rules:Note that the last manipulation, 1+1=1,differs from the ordinary arithmetic use of the +sign.As in ordinary algebra, parentheses may be used in boolean expressions to group terms and give precedence to operations. If these are no parentheses, the AND functions in an equation are evaluated first.一个不错的数字业务的特点是，输入输出变量值的完整集合可以写下来。图5.3（a）显示这样的函数表，相应的方程C = AB公司，其中列出了从这个功能表输入变量A和B共同所有可能的组合对应的输出变量与正我们看到，在代数方面的AND运算是一个乘法的形式，这些操作规则：的定义或操作：由于D和E两个输入和输出变量楼的表达式F = D或E指女= 1如果D或E = 1 = 1或两个，均为D = 1和E = 1+号是用作或速记，并永远不会忽略的代数表达式，因此，Eq.5.5写为F = D的代数+ 图5.3（b）所示的逻辑符号的双输入或门连同相应的功能表中使用。代数，或操作的是一种特殊形式进行除依照本规则：注意最后的操纵，1 +1 = 1，从普通的算术+符号使用不同。由于在普通代数，括号可用于布尔表达式组方面，给予优先考虑操作。如果这些是没有括号，在方程和函数首先计算。Definition of the NOT operation: In some situations, the opposite value of a particular variable is required. In Boolean algebra, the opposite value of a variable is called the complement of that variable, and is denoted by a bar drawn over the variable in question. The complement operation is summarized below using variable G as an example .The logic operation that produces the complement is called inversion, or the NOT operation. The logic symbol and function table for an inverter is shown is Figure 5.3(c). De Morgans Theorem. De Morgans theorem is a Boolean algebra identity expression that states or equivalently(Note that the complete algebraic expression underneath the complement bar must first be evaluated, then the complement taken.) This theorem is easily verified by examining the function tables for the two sides of each equation. NOT运算的定义：在某些情况下，对面的一个特定变量的值是必需的。在布尔代数中，一个变量的相对值称为该变量的补充，并得到了有关变量绘制一个酒吧表示。补操作总结如下使用为例变量克。在逻辑运算，从而产生补充被称为反转，或不操作。其中的逻辑符号和一个逆变器的功能表显示的是图5.3（c）项。德摩根定理。德摩根定理是一个布尔表达式，代数身份国家或等价（注意：完成下面的补充栏必须先进行评估，然后采取补代数表达式。）这个定理是很容易通过检查每个方程为双方的函数表核实。In summary, De Morgans theorem states that the complement of the OR operation is equivalent to performing the AND operation on the complement variables, and vice versa. De Morgans theorem is of great use in manipulating and simplifying Boolean algebraic expression that contain more than one basic logic operation .The composite operations NAND and NOR. Two combinations of basic operations arise so often that they are given individual names and logic symbols. The NOR operation is the complement of the OR operation (the name is simply a contraction of “NOT OR”), and is defined by or , by De Morgans theorem,总之，德摩根定理指出的补等于或操作上执行的补充变量和操作，反之亦然。德摩根定理是在大量使用，简化操作布尔代数表达式包含多个基本的逻辑运算。该复合操作的NAND和NOR。两个基本操作的组合出现，常常使他们获得个人姓名和逻辑符号。在NOR型经营是补充的或运算（名称只是一个“不或”）收缩，定义为或由德摩根定理，Two equivalent symbols for the NOR gate, representing Eq.5.9 and Eq5.10 respectively, are shown in Figure5.4(a) along with the NOR function table. Note that the small circle adjacent to the input or output of the basic gate symbols produces the INVERSION of the variable in each case.The complement of the AND operation is called the NAND operation (from “NOT AND”), and is defined by the two equivalent forms or The two equivalent symbols for NAND gates and the function table are shown in Figure 5.4(b).两个等价符号或非门，分别代表Eq.5.9和Eq5.10，载于Figure5.4（1）随着NOR型函数表。请注意，小圆圈旁输入或输出生产基本门符号在每个案件中的变量反演。的补，操作所谓的NAND操作（从“不和”），是由两个等价形式定义或这两个非门和函数表相当于符号如图5.4（b）项。The principal importance of NOR and NAND is that they are the simplest logic functions to construct in integrated circuit form. Thus, while it may be easier for the beginner to learn to “think” with OR and AND , he should also practice thinking with NOR and NAND as these functions are likely to be used in the final circuit realization. Also, it is possible to synthesize all of the logic functions using only NOR gates or only NAND gates . Let us formulate a simple everyday situation in terms of digital variables and Boolean operations. Suppose you are driving home and become thirsty for a hot drink. You see a diner ahead and pull in . Let us develop a Boolean equation for whether or not you obtain a drink. The first step is to assign variables for the problem: The diner is open for business = D=1, or simple D (=means implies)The diner sells coffee =CThe diner sells tea =TYou get a drink =XThe next step is to use AND and OR operations to construct this Boolean equation: Or omitting the dot Which is equivalent to 主要重要性的NOR和NAND是他们最简单的逻辑功能，构建在集成电路形式。因此，虽然它可能会更容易为初学者学习“思考的OR和AND”，他也应该实践的NOR和NAND的思想，因为这些功能可能会在最终电路实现使用。此外，它可以合成的或非门的逻辑只使用或只与非门的所有功能。让我们在制订数字变量和布尔操作方面简单的日常生活情况。假设你是开车回家，并为热饮成为渴。您看到一个小餐馆前面拉英寸让我们制定一个你是否取得喝布尔方程。第一步是分配的问题变量：该餐馆是开业=“ = 1，或简单（=”手段暗示）该餐馆出售的咖啡=“销售茶叶的晚餐=“你去喝点水=“X下一步是使用AND和OR操作兴建此布尔方程：或省略点这相当于The final step is to construct a logic flow diagram using gate symbols. Two possible logic flow diagrams, corresponding to Eq.5.16 and Eq.5.17 are shown in Figure 5.5. As an illustration of how only NOR gates or only NAND gates can be used to synthesize any function, two additional implementation of this same example are shown in Figure 5.6, Notice that when both inputs of the two-input NOR gate are connected together ,as in Figure 5.6(a), the gate becomes an inverter.Flip-Flop from Logic Gates The flip-flop (abbreviated FF) is a logic circuit with two outputs, which are the inverse of each other, which outputs as Q and . The Q output is called the normal FF output and is the inverted FF output. When a FF is said to be in the high (1)state or the low(0) state, this is the condition at the Q output. Of course, the output is always the inverse of Q .There are two possible operating states for the FF: (a) Q=0, =1; and (b) Q=1, =0. The FF has one or more inputs, which are tied to cause the FF to switch back and forth between these two states. As we shall see, once an input signal causes a FF to go to a given state, the FF will remain in that state even after that input signal is terminated. This is its memory characteristic. A basic FF circuit can be constructed from two NOR gates connected as shown in the Figure 5.7. Notice that the output of NOR-1 serves as one of the inputs to NOR-2, and vice versa. The two output are Q and , which are always the inverse of one another during normal operation. The two inputs are labeled SET and CLEAR, for reasons that will soon apparent.最后一步是建立一个逻辑流程图用门符号。两个可能的逻辑流程图，对应Eq.5.16和Eq.5.17如图5.5所示。作为一个如何的NOR闸或只与非门可以用来合成任何职能画像，这两个同样的例子额外implementation见图5.6，Notice，当了二输入或非门两个输入连接在一起，作为在图5.6（a）条，门成为一个逆变器。触发器的逻辑门触发器（简称法郎）是一个具有两个输出，这是对方，作为Q输出和反逻辑电路。所谓的Q输出是正常的法郎输出，倒法郎输出。当FF是说是在高（1）国家或低（0）状态，这是在Q输出条件。当然，输出始终是Q的逆。有两个可能的运行状态的FF：（1）问= 0 = 1;及（b）问= 1，= 0。该法郎有一个或多个输入，这是导致挂钩FF到这两种状态之间进行切换来回。正如我们将会看到，一旦输入信号导致法郎到一个给定的状态，法郎将在该州仍然即使该输入信号被终止。这是它的记忆特性。一个基本的电路可以法郎建造，在香港如图5.7所示连接两个或非门。请注意的NOR - 1的输出作为输入1的NOR - 2，反之亦然。两个输出是Q和，总是一个在正常运作另一个逆。这两个输入标记设置和清除，原因是什么将很快显现。Let us begin our analysis of the NOR FF circuit by making both inputs low (SET=CLEAR=0). In this situation we cannot determine what the Q and output values are since there are two, equally likely, possibilities: (a) Q=0, =1, and (b) Q=1, =0. To verify this, let us first assume that Q is 0. This 0 and the 0 from the SET input produce a 1 at the NOR-1 output, thereby making Q=1(recall that a NOR output is 1 only when all its inputs are 0). This Q=1 is fed to the NOR-2 input, thereby producing a 0 at its output; so Q=0, as was originally assumed.Now, let us assume instead that Q=1.This 1 applied to NOR-1produce a 0 at its output, so Q=0. The Q=0 is fed to NOR-2 together with the 0 from the CLEAR input, thereby producing a 1 at its output; so Q=1,as was originally assumed.Thus, with SET and CLEAR both 0, the FF outputs can be in either state. Actually, the FF output state will depend on what has previously occurred at the inputs. The SET=CLEAR=0 condition will not affect the FF outputs; they will simply remain in whatever state they happen to be in at the time. This is the first case shown in the table and represents the “normal” state. In other words, the SET and CLEAR inputs are normally in the 0 state.To make the FF go to a specific state, we must put a 1 on the appropriate input. To make Q=1, we must apply a 1 to the SET while keeping CLEAR=0. The 1 at the SET input causes NOR-1 to go 0, so Q=0. This 0 fed to NOR-2 along with CLEAR=0 causes NOR-2 to produce Q=1. 让我们开始制作都投入低（集=清除= 0），我们的NOR电路分析法郎。在这种情况下，我们不能确定什么Q和输出值，是因为有两个，同样有可能，可能性：（1）问= 0，= 1，（二）问= 1，= 0。为了验证这一点，让我们先假设Q为0。这从0 SET输入0出示了NOR - 1输出为1，从而为Q = 1（记得，输出为1的NOR只有当所有的输入0）。这是美联储为Q = 1到了NOR - 2的投入，从而在输出端产生一个0，所以为Q = 0，如最初设想。 现在，让我们假设，而不是使Q = 1，本一适用于NOR型1produce在其输出为0，所以为Q = 0。在Q = 0是美联储的NOR - 2一起从CLEAR输入0，从而产生在其输出为1，所以为Q = 1，原来承担。 因此，在设置和清除均为0，整个FF输出可以在任何一国。其实，法郎输出状态将取决于我们在以前发生的投入。在SET =清除= 0的条件，不会影响法郎产出，他们会简单地停留在任何国家，他们将在发生时间较长。这是第一例在表中显示，代表了“正常”状态。换句话说，输入的设置和清除，通常在0的状态。 为了使法郎转到一个特定的国家，我们必须放在适当的投入为1。为了使为Q = 1，我们必须申请1至设定的同时保持清除= 0。 1在设定输入导致的NOR - 1去0，所以为Q = 0。这0美联储的NOR - 2 = 0清除沿着原因的NOR - 2生产为Q = 1。 Thus, a 1 on the SET input (while CLEAR=0) will always produce Q=1( =0). This 1 need only be present long enough to allow the gates to respond and pass the signal. When SET returns to 0, so that both inputs are 0,the FF will remain in the Q=1 state. This is the second case listed in the table.Clearly, since the circuit is completely symmetrical, it can be seen that a 1 applied to the CLEAR input while SET=0 will produce a FF output state of Q=0( =1). When the CLEAR input returns to 0, the FF will remain in the Q=0 state. This is the third case listed in the table.The last case to consider is SET=CLEAR=1,This condition will produce 0 at the output of both NOR gates, so Q=0 and =0. This is obviously an illegal condition if it is desired that the FF outputs be the inverse of each other. Furthermore, when the inputs are returned to 0, the FF output state will depend on which input reaches 0 first. This makes the SET=CLEAR=1 condition ambiguous. For these reasons the latter case is never purposely used during the operation of this type of FF.因此，1对SET输入（同时清除= 0）将始终产生为Q = 1（= 0）。这1只需要足够长的时间，使目前的大门作出回应，并通过信号。当SET返回为0，这两个输入是0的话，将继续留在了FF的Q = 1的状态。这是第二种情况表中列出。显然，由于电路完全对称的，可以看到，一个1适用于有明确的输入，同时集= 0将产生一个输出状态的Q法郎= 0（= 1）。当CLEAR输入返回为0，将继续留在法郎的Q = 0的状态。这是第三种情况表中列出。最后一种情况下要考虑的是集=清除= 1，这种情况会产生在两个或非门输出0，所以Q二0= 0。这显然是非法的条件，如果它是理想的法郎产出是相互逆。此外，当输入返回到0时，输出状态法郎将取决于它输入到0首。这使得在SET =清除= 1条件含糊不清。基于这些原因，后一种情况下是没有特意在这次的FF式操作使用。The SET-CLEAR(S-C) Flip-Flop The FF circuits described above are examples of SET-CLEAR (S-C) flip-flops. The general logic symbols used to represent the S-C FF are shown in the Figure5.8 with their corresponding truth tables. The figure (a) represents the S-C FF that responds to high levels on its S and C inputs, such as the NOR-gate FF. And the Figure (b) represents the S-C FF that responds to low levels on its S and C inputs, such as the NAND-gate FF. Note the small circles shown on the S and C inputs to indicate that this FF responds to 0s on these inputs. We shall generally use these block symbols to represent S-C FFs instead of showing the complete internal circuitry. The S-C flip-flop forms the basis for many other types of flip-flop circuits. By itself the S-C FF is useful as a memory element to store information. To illustrate, the Figure 5.9 shows a simple burglar alarm circuit using a S-C FF.The FF is initially in the Q=0 state, so the alarm is deactivated. With the photocell illuminated, the transistor is saturated, so Vx=0, applying a low to the S input. If the photocell goes dark, the transistor is turned off and Vx=5V, This applies a high to the S input, causing the FF to go to the Q=1 state, thereby activating the alarm. The FF, once it has been set to Q=1, will stay there (acts memory) even if the photocell immediately goes light again. Thus, the alarm will persist until the FF is cleared to the Q=0 state by applying a momentary 1 to the C input. 在设置清除（第S -丙）触发器 上述电路的法郎，是集清晰（SC）的触发器的例子。一般的逻辑符号来表示的SC法郎是在与其相应的真值表Figure5.8所示。这个数字（1）代表资深大律师法郎，响应其S和C的高层次，如或非门法郎投入。 而图（二）代表资深大律师法郎，响应其S和C水平低，如与非门法郎的投入。注意：显示在S和C的投入，这表明法郎回应0年代就这些投入的小圆圈。一般我们会使用这些符号来代表资深大律师块农民田间学校，而不是显示了完整的内部电路。 常设委员会触发器构成的触发器电路，许多其他类型的基础。通过自身的SC FF是有用的作为一个存储单元来存储信息。为了说明这一点，图5.9显示了一个简单的防盗报警器电路使用一个资深大律师法郎。 在最初的法郎的Q = 0的状态，所以报警停用。随着光电照明，晶体管饱和，所以Vx的= 0，采用低到S输入。如果光电熄灭，晶体管处于关闭状态和VX = 5V时，这适用于高的S输入，导致法郎去到Q = 1的状态，从而激活了警钟。该法郎，一旦它被设置到Q = 1，将呆在那里（行为内存），即使光线的光电池立即去了。因此，警报将持续到法郎被清除到Q采用一时一到C = 0的输入状态。 The Clocked S-C Flip-FlopMost digital systems operate as synchronous sequential systems. What this means is that the sequence of operations that takes place is synchronized by a master clock signal, which generates periodic pulses that are distributed to all parts of the system. This clock signal is usually one of the forms shown in the following Figure 5.10, very often it is a square wave (50 per cent duty cycle), such as the one shown in the figure (b).The clock signal is the signal that causes things to happen at regularly spaced intervals. In particular, operations in the system are made to take place at times when the clock signal is making a transition from 0 to 1 or from 1 to 0. These transition times are pointed out in the figure. The 0-to-1 transition is called the rising edge or positive-going edge of the clock signal; the 1-to-0 transition is called the falling edge or negative-going edge of the clock signal. The synchronizing action of the clock signal is the result of using clocked flip-flop, which are designed to change states on either (but not both) the rising edge or the falling edge of the clock signal. In other words, the clocked FFs will change states at the appropriate clock transition and will rest between successive clock pulses. The frequency of the clock pulses is generally determined by how long it takes the FFs and gates in the circuit to respond to the level changes initiated by the clock pulse, that is, the propagation delays of the various logic circuits.该时钟的S - 触发器 大多数数字系统同步连续运作系统。这意味着该业务发生的顺序是由主时钟信号，产生的是分配给该系统的所有部件周期脉冲同步。这个时钟信号通常是在以下图5.10，很多时候它是一个方波占空比百分之五十（）所示的形式，如在图（所示的，一架B）。 该时钟信号是信号，导致事情发生在定期间隔时间。尤其是，业务系统是由以发生时间时，时钟信号正在从0到1或1到0的过渡。这些过渡时期，指出了在图中。 0比1的过渡称为上升沿或正持续在时钟信号边缘的1到0的过渡称为下降沿或负向的时钟信号边沿。 在时钟信号同步行动是使用频率触发器，其目的是为了改变国家的结果是（但不能同时）的上升沿或下降沿的时钟信号。换句话说，农民田间学校的时钟将在适当的改变时钟过渡态和休息之间将连续时钟脉冲。 在时钟脉冲的频率一般是确定需要多久才能在农民田间学校和门电路的响应水平变化的时钟脉冲启动，即在各种逻辑电路的传输延迟。The above Figure5.11(a)shows the logic symbol for