数字集成电路分析与设计第四章答案.doc

Chapter 4P4.1. Problem should refer to Figure P4.2.a. All inverters but the CMOS inverter consume static power then the output is high. Notice that in the first three inverters when the input is high, there is always a direct connection from VDD to GND.b. None of the static inverters consumes power when the input is low because there is no path from VDD to GND.c. All inverters but the saturated enhancement inverter has a VOH of 1.2 V.d. Only the CMOS inverter has a VOL of 0 V.e. Except for the CMOS inverter, all the other inverters functionality depend on the relative sizes of the transistors.P4.2. Problem should refer to Figure P4.1a. Resistive loadb. Saturated-enhancement loadIterate to produce:To compute VOL we can ignore body effect and equate currents:Solve for c. Linear-enhancement loadIterate to produce:This tells us that VGG should have been above 1.6V (closer to 1.7 V).To compute VOL we can ignore body effect and equate currents. Note that the load is saturated even though we call it a linear-enhancement load. The driver is also saturated due to the device sizes used.Solve for d. CMOS P4.3. For this problem, you are required to use the formulae: We already know that VOH=1.2 V and VOL=0 V. For VS use:Next VIL and VIH are estimated as follows:Therefore When we cut the size of the PMOS device in half, the VTC shifts to the left. So VIL, VS, and VIH will all shift to the left. The recalculation of the switching threshold produces VS=0.566V.We can compute VIL to be roughly 0.533V and VIH to be roughly 0.667V.Therefore P4.4. Similar approach as in P4.3. Run SPICE to check results.P4.5. First, set up the equation.Now solve for .This implies that a very large (W/L)P is needed to reach the desired value. It also reveals the limitations of the models. SPICE would be needed to obtain an acceptable solution if the switching threshold of 0.9V is truly desired.P4.6. SPICEP4.7. The advantages of the pseudo-PMOS is that it can reach a VOH of VDD while the pseudo-NMOS VOH can never reach that value. Additionally, the pseudo-NMOSs VOH depends on the relative sizings of the inverters.The disadvantage is the dual of its advantage. The pseudo-PMOS inverter can never reach a VOL of 0 V. In addition, the pseudo-PMOS device will have to be approximately twice as large as a pseudo-NMOS device with comparable characteristics. This is due to the unequal mobility of holes and electrons. The pseudo-PMOSs NMOS pull-down device is twice as strong as the pseudo-NMOSs PMOS pull-up device, that means that the pseudo-PMOSs PMOS will have to be bigger than the NMOS device in a pseudo-NMOS.P4.8. a) Circuit is a buffer with degraded outputs.Output swing calculation:When , output voltage is . Since the source of NMOS transistor is not connected to substrate (ground), we must take into account body effect.When , output voltage is . Since the source of PMOS transistor is not connected to substrate (VDD), we must take into account body effect.Therefore the output swing is to with full accounting for body effect.b) Assume that the input is at 0 and the output is at |VTP|. As the input is increased, the output will stay constant until the NMOS device turns on. That will occur at VIN=|VTP|+VTN. The upper transistor behaves as a source follower and will pull the output along as the input rises until the output reaches VDD-VTN. However, as the input is reduced in value the output stays at its high value until the PMOS device turns on. This occurs at VIN=VDD-( |VTP|+VTN). Then the PMOS device acts as a source follower and the output drops linearly to |VTP| as the input is reduced.c) The gain of the circuit is close to unity but slightly below this value. The circuit has poor noise rejection properties as it lacks the regenerative properties (this is a consequence of low gain).d) SPICE run.P4.9. Resistive Load inverter:Saturated Enhancement Load inverter (ignoring body-effect):Linear Enhancement Load inverter (ignoring body-effect):The linear enhancement load inverter requires the largest pull-down device since it has the strongest pull up device. The resistive load inverter is next and the saturated enhancement load requires the smallest pull-down device.P4.10. We will illustrate the process and estimate the solutions for this problem.We already know that VOH=1.2 V and VOL=0 V. For VS use:Next VIL and VIH are estimated as follows:We can compute VIL to be roughly 0.533V.We can compute VIH to be roughly 0.667V.When we double the size of the PMOS device, the VTC shifts to the right. So VIL, VS, and VIH will all shift to the right. The recalculation of the switching threshold produces VS=0.6V.We can compute VIL to be roughly 0.55V and VIH to be roughly 0.65V.P4.11. The peak current would occur when both devices are in saturation and when Vout=Vin=VS. We can easily compute VS as:P4.12. As the required VOL becomes smaller, the WD/WL ratio becomes larger.P4.13. SPICEP4.14. The expression for the switching threshold of a CMOS inverter is:a.Solving for .Now solving for the ratio of sizes.b.Solving for .Now solving for the ratio of sizes.In the first case (), the PMOS is much larger than the NMOS, so tPLH is smaller and tPHL is larger. The reverse is true for the second case.P4.15 (a) It does not have the regenerative property since the gain is less than one. (b) The last inverter would have an output of about 0.8V. (c) It is not possible to define the noise margin for this gate. Even a proper input eventually produces the incorrect output.P4.16 Both gates wou